Patents by Inventor John G. Jansen

John G. Jansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logic-based eDRAM using local interconnects to reduce impact of extension contact parasitics
    Patent number: 8283713
    Abstract: An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: October 9, 2012
    Assignee: LSI Corporation
    Inventors: John G. Jansen, Chi-Yi Kao, Ce Chen, Shahriar Moinian
  • LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS
    Publication number: 20110298026
    Abstract: An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.
    Type: Application
    Filed: March 14, 2011
    Publication date: December 8, 2011
    Applicant: LSI Corporation
    Inventors: John G. Jansen, Chi-Yi Kao, Ce Chen, Shahriar Moinian