Abstract: A lithography and etching method for forming an alignment mark (104) and at least one device feature (such as a shallow trench 105) on a wafer (99) is provided. The etching process (18) comprises: a first etching step (1811) for pre-defining at least one alignment mark (103) and a second etching step (1812) for defining desired semiconductor device patterns (such as a shallow trench 105) on said wafer surface and completing said at least one alignment mark (104).

Abstract: A lithography and etching method for forming an alignment mark (104) and at least one device feature (such as a shallow trench 105) on a wafer (99) is provided. The etching process (18) comprises: a first etching step (1811) for pre-defining at least one alignment mark (103) and a second etching step (1812) for defining desired semiconductor device patterns (such as a shallow trench 105) on said wafer surface and completing said at least one alignment mark (104).

Abstract: The present invention generally relates to a method for controlling the temperature of a substantially flat object and to a temperature-controlled chuck comprising a chuck body (20) having an object support side (21) and a back side (22). Said object support side (21) holds a substantially flat object (1) having a front side (2) and a back side (3) on said back side (3) of said object (1). A plurality of temperature sensing elements (4) is distributed on said object support side (1) to measure the temperature distribution of said flat object (1). A plurality of individual temperature influencing elements (6; 8; 9) is distributed on said object support side (21) to face said back side (3) of said flat object (1), each of said temperature influencing elements (6; 8; 9) being arranged to influence the temperature of a partial area of said object's back side (3) as desired.

Abstract: The present invention generally relates to a method for controlling the temperature of a substantially flat object and to a temperature-controlled chuck comprising a chuck body (20) having an object support side (21) and a back side (22). Said object support side (21) holds a substantially flat object (1) having a front side (2) and a back side (3) on said back side (3) of said object (1). A plurality of temperature sensing elements (4) is distributed on said object support side (1) to measure the temperature distribution of said flat object (1). A plurality of individual temperature influencing elements (6; 8; 9) is distributed on said object support side (21) to face said back side (3) of said flat object (1), each of said temperature influencing elements (6; 8; 9) being arranged to influence the temperature of a partial area of said object's back side (3) as desired.

Abstract: A method of forming structures on a semiconductor wafer (1) by lithographic and subsequent ion implant steps comprises the steps of: deposition of a resist layer (5) on a surface of said semiconductor wafer (1), exposing said resist layer to light of a predetermined wavelength through a reticle and an optical system so as to form an image of said reticle on said semiconductor surface, developing and cleansing said surface of said semiconductor wafer (1) so as to remove at least partly said resist layer (5) depending on whether or not said resist layer had been exposed, implantation of ions so as to determine the conductivity of said semiconductor in said cleansed areas of said semiconductor surface. In order to allow the preparation of the resist for all doping profiles in a single processing step it is suggested that the surface energy of the resist (5) vs.

Abstract: A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.