Patents by Inventor John G. Mathieson

John G. Mathieson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6847365
    Abstract: A media processing system is provided including a DRAM that includes a plurality of storage locations for storing digital data being processed by said media processing system, said digital data including video data that is compressed in a standardized format, a system for processing said digital data that includes said standardized format compressed video data to produce compressed video images and image data, a system for decoding said standardized format compressed video images to generate full motion video pixel data, a system for sharing said DRAM between said processing means and said decoding means, and a system for producing a full motion video signal from said full motion video pixel data. The media processing system may also have a system for multiplying or combining a first pixel by a second pixel in a single clock cycle.
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: January 25, 2005
    Assignee: Genesis Microchip Inc.
    Inventors: Richard G. Miller, Louis A. Cardillo, John G. Mathieson, Eric R. Smith
  • Patent number: 6732210
    Abstract: In accordance with the invention, a multi-processing unit system including a plurality of processing units in direct communication via a communication bus is presented. The system includes a communication bus arbiter having a communication packet multiplexer. Each of the processing units include a communication bus interface comprising a transmitter interface and a receiver interface. Each of the transmitter interfaces are connected to the communication packet multiplexer of the communication bus arbiter via separate 32-bit interfaces. Each of the receiver interfaces is connected to the communication packet multiplexer of the communication bus arbiter via a single 32-bit bus. The system may further comprise a first control signal connection means for communicating control signals between the transmitter interface and the communication bus arbiter and a second control signal connection means for communicating control signal between the receiver interface and the communication bus arbiter.
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: May 4, 2004
    Assignee: Genesis Microchip INC
    Inventor: John G. Mathieson
  • Patent number: 5819058
    Abstract: A system and method for compressing and decompressing variable length instructions contained in variable length instruction packets in a processor having a plurality of processing units is provided that has a compression system with a system for generating an instruction packet containing a plurality of instructions, a system for assigning a compressed instruction having a predetermined length to an instruction within the instruction packet, a shorter compressed instruction corresponding to a more frequently used instruction, and a system for generating an instruction packet containing compressed instructions for corresponding ones of said processing units.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: October 6, 1998
    Assignee: VM Labs, Inc.
    Inventors: Richard G. Miller, Louis A. Cardillo, John G. Mathieson, Eric R. Smith