Abstract: In accordance with one aspect of the invention, a method is provided for identifying multiple, series-connected pass FETs in an integrated circuit, by evaluating a current node in the netlist to determine whether the current node is a static gate input (or output). If the node is that of a pass gate input (or output), the method then identifies at least one pass FET that is channel-connected to the current node, and determines that an output node (input node) of the at least one pass FET is the same node as the current node. Thereafter, the method reassigns the current node to be an input node (output node) of the at least one pass FET, and repeats the foregoing steps (beginning with identifying at least one pass FET that is channel-connected to the current node). In accordance with another aspect of the present invention, a system is provided for identifying multiple, series-connected pass FETs in an integrated circuit by evaluating a netlist.

Abstract: The present invention is generally directed to a system and method for efficiently evaluating a design quality of a circuit defined by a netlist. An inventive method includes the steps of creating an element data structure for each circuit element in the netlist, wherein the data structure of a given element defines a plurality of physical characteristics for the element, and creating a node data structure for each circuit node in the netlist, wherein the data structure of a given node defines a plurality of physical characteristics for the node. Thereafter, the method determines a TRUE/FALSE value for the physical characteristics for entries within both the element data structure and the node data structure. Finally, the method records the determined TRUE/FALSE values for later retrieval. An inventive system includes an element data structure for defining each circuit element in the netlist, wherein the data structure of a given element defines a plurality of characteristics for the element.

Abstract: The present invention is generally directed to a system and method for approximating the coupling cross- a node in a circuit and determining whether the coupling voltage noise exceeds a permissible value. In accordance with one aspect of the invention, a method uses a first circuit model to obtain a total resistance value of a conductor extending between a driver configured to drive the node and a receiver, and uses a second circuit model to determine a total capacitance. The method also determines an aggressor coupling capacitance between the node and an aggressor signal using at least one criteria, and computes a ground capacitance by subtracting the aggressor coupling capacitance from the total capacitance. The method also determines the effective resistance of the driver, and a weighted average rise time for all aggressor signals on the node.

Abstract: The present invention is generally directed to a system and method for identifying a storage node that is susceptible to charge sharing by another node. In accordance with one aspect of the invention, a method identifies storage nodes susceptible to charge sharing by first identifying, from a netlist, a storage node. For a given storage node, the method determines whether any pass FET devices are being driven by the storage node. For any such pass FET devices, the method retrieves a capacitance value for both sides of the pass FET devices being driven by the storage node. Specifically, a first capacitance value is retrieved for the storage node side of each pass FET device, and a second capacitance value is retrieved for a node on the opposite side of each pass FET device. Then the method calculates a ratio between the first and second capacitance values for each pass FET device being driven by the storage node.

Abstract: The present invention is generally directed to a system and method for evaluating the loading of a clock driver. Specifically, the present invention operates by evaluating a netlist file of a circuit. In accordance with one aspect of the present invention, a method evaluates each node within a netlist file to determine: (1) whether that node is an output node for a clock driver; and (2) for clock driver nodes, whether that node is within loading specification for the particular clock driver circuit. In accordance with one embodiment of the invention, the method operates by identifying a clock driver output node, calculating a PFET: NFET ratio of the clock driver output node, determining a “category” of the clock driver output node, obtaining a load on the clock driver output node, and determining whether the load is within specification for the clock driver circuit.

Abstract: The present invention is directed to a system and method for identifying multiplexers from a netlist. In accordance with one aspect of the invention, a method identifies multiplexers from a netlist by identifying both an input node and an output node of a pass gate. The method then identifies all FETs that are channel connected to the output node, and evaluates all FETs that are identified as being channel connected to the output node, to determine whether they are pass FETs. Finally, the method determines whether at least one of the identified pass FETs has an output that is the same node as the output node and an input that is not the same node as the input node. In accordance with another aspect of the invention, the method identifies a node in the netlist that is an output node of a first pass FET and identifies at least one other pass FET that has an output that is the same node as the output node.

Abstract: In accordance with one aspect of the invention, a method evaluates an element of the netlist, and ensures that a gate node of the element is defined as a clock node. Then, the method determines whether a first channel node of the element has already been designated as a clock node. If not, the method determines that the clock signal should be propagated through the element, and marks the first channel node as a clock node. Thereafter, the method evaluates another element that is gate connected to the first channel node, and repeats the above-listed steps on the another element. In accordance with another aspect of the invention, a method evaluates an element of the netlist, ensures that a gate node of the element is defined as a clock node, ensures that a channel node (either source or drain) of the element is not a precharge node, and ensures that the channel node of the element is not a predischarge node.

Abstract: In accordance with one aspect of the invention, a method identifies all NFETs that are impermissibly interposed in a pull up path. The method includes the steps of identifying an output node in a netlist file and identifying as pull-up paths all channel-paths extending between the output node and VDD. Then, the method evaluates every element along each of the identified pull-up paths to determine whether any element is an NFET, and generates an error message for any NFET identified along a pull-up path, if the NFET is neither channel connected to an interstitial pre-charge node nor a pass FET. In accordance with another aspect of the invention, a method identifies all PFETs that are impermissibly interposed between an output node and Ground. In accordance with this aspect, the method identifies an output node in a netlist file and identifies, as pull-down paths, all channel-paths extending between the output node and Ground.

Abstract: The present invention is generally directed to a system and method for evaluating a netlist of a schematic to detect the output of a clock driver. In accordance with one embodiment of the invention, a method is provided for determining whether a circuit node is an output node of a clock driver circuit. The method includes the steps of ensuring that the node is a clock node, ensuring that the node is a node within an inverter loop, identifying every FET that is channel connected to the node, and, for every identified FET, ensuring that a signal that drives a gate node of the FET also drives a gate node of a different type FET. With these primary tests satisfied, the method determines the node under consideration to be an output node of a clock driver circuit. In accordance with another aspect of the invention, a method determines whether a circuit node is an output node of a clock driver circuit by ensuring that the node is a node within an inverter loop, and ensuring that a gate node of every FET (i.e.

Abstract: A method and apparatus for generating a database to be utilized by a rules checker for evaluating the quality of a particular design, such as, for example, an integrated circuit design. The design to be evaluated comprises a plurality of elements coupled together by at least one node. The apparatus of the present invention comprises a computer running a database generation program which receives, as its input to the database generation program, information relating to characteristics of the elements and nodes. The database generation program utilizes the input to produce a data structure for each of the elements and nodes. These data structures comprise the database which can be utilized by the rules checker to evaluate the quality of the design. In accordance with the preferred embodiment of the present invention, the input to the database generation program corresponds to the output of a timing analyzer program which is being executed by the computer.

Abstract: A method and apparatus for detecting a predischarge node in an integrated circuit. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether a predischarge node exists in the integrated circuit. The rules checker program evaluates each node in the integrated circuit and determines whether or not an N field effect transistor (NFET) is connected to the node and, if so, whether the gate terminal of the NFET is connected to a clock and whether a drain or source terminal of the NFET is connected to ground. The rules checker program also determines whether or not a P field effect transistor (PFET) is connected to the node being evaluated and, if so, whether it has a gate terminal which is not connected to a clock and drain and source terminals which are not connected to a supply.

Abstract: The present invention is generally directed to a system and method for evaluating a netlist of a schematic to detect circuit configurations that are susceptible to bootstrapping. In accordance with one aspect of the present invention, a method is provided for detecting n-type field effect transistors (NFETs) that are susceptible to bootstrapping. The method operates by evaluating at least one NMET in a netlist and ensuring that the at least one NFET is not channel connected to ground. The method further ensures that a gate node of the at least one NFET is connected to a channel node of a PFET. In accordance with a similar aspect of the present invention, a method is provided for detecting p-type field effect transistors (PFETs) that are susceptible to bootstrapping. The method operates by evaluating at least one PFET in a netlist and ensuring that the at least one PFET is not channel connected to VDD.

Abstract: To achieve the advantages and novel features, the present invention is generally directed to a system and method for identifying pass FETs from a netlist. In accordance with one aspect of the invention, a method identifies pass FETs from a netlist by identifying complementary pass FET circuit configurations at each node, identifying RAM pass FET circuit configurations at the node, and identifying single pass FET circuit configurations at the node. In accordance with another aspect of the invention, a system is provided for identifying pass FETs connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for identifying complementary pass FET circuit configurations at the node, a code segment for identifying RAM pass FET circuit configurations at the node, and a code segment for identifying single pass FET circuit configurations at the node.

Abstract: A method is provided for identifying a NOR gate from a netlist. The method operates by first identifying at least one static gate output node, and then, for that at least one static gate output node, evaluating all channel-connected field effect transistors (FETs) that are electrically connected to the at least one static gate output node to ensure that: (i) no PFET (p-channel FET) that is channel connected to the at least one static gate output node is directly connected to VDD, (ii) all NFETs (n-channel FETs) that are channel connected to drive the at least one static gate output node are directly connected to ground, and (iii) at least one PFET and at least one NFET are channel connected to the at least one output node.

Abstract: A rules checking methodology ensures the quality of a structure or system having one or more elements and one or more nodes that serve as connection points to the elements. The rules checking methodology examines the elements and nodes of the structure and makes decisions regarding the quality of the structure according to parameters, or rules, provided.

Abstract: A cache output selector for a multi-way set-associative cache memory which provides for simultaneous access of multiple-word data is presented. The cache memory comprises a plurality of data arrays wherein no two consecutive multiple-word reside in the same data. The cache output selector of the present invention includes, for each data array of the plurality of data arrays, a qualifying multiplexor which receives the respective tag match signals from each of the tag matching circuits as data input and a set selector signal, as selector input, and at least one qualifying signal as qualifying input. The set selector signal indicates which data array a first set of the multi-way set-associative memory resides in during a current read/write cycle. The qualifying multiplexor combines a clock qualifying functionality and a multiplexor functionality to produce a data array output enable signal in only two levels of logic.

Abstract: Disclosed herein are methods and apparatus relating to speed optimal bit ordering in a cache memory. All of the data arrays capable of driving a single output bit are grouped with combinational I/O logic for driving same. The data arrays and combinational I/O logic corresponding to a single output bit can be thought of as a bit slice of a cache. Bit slices are preferably arranged so that predecode bit slices are nearest to the I/O end of the cache. A number of predecode bit slices corresponding to a single instruction or data word are preferably followed by the instruction's predecode data bit slices. Non-predecode data bit slices are arranged so that big/little endien data bit pairs are adjacent to one another, or as close to each other as possible given other bit slice ordering restraints. The arrangement of bit slices in big/little endien pairs yields I/O buses of minimum length. Components of combinational I/O logic are arranged in staggered form, perpendicularly to the I/O datapath of a cache.

Abstract: A dynamic tag match circuit (10) has exclusive-OR gates (18) each of which receives one bit of an address signal (A) from cache tag RAM, an inverted bit of the address signal (NA) from the cache tag RAM, and one bit of an address signal (B) from an address translator. The exclusive-OR gates (18) are in parallel to each other and output a hit signal which is low only when a match occurs between the two address signals. Additionally, the hit signal is low only when the results of a force miss circuit (14) indicate that a force miss should not occur. The dynamic tag match circuit (10) further has a pull-up circuit (16) for precharging the output of the circuit (16) and for holding the output of the circuit (16) at one of the two logical levels. The force miss circuit (14) advantageously incorporates logic which coordinates the timing of the force miss evaluation with the arrival of the address (A) from the cache tag RAM.

Abstract: A multi-purpose shadow register apparatus in a computer system having a central processing unit, a memory, a memory output select circuit, and a memory output bus includes a shadow register in parallel with the memory output select circuit. The shadow register is connected to receive memory output data from the memory output bus and is responsive to an output enable signal to provide shadow register output data on a shadow register output bus. A shadow register functional logic block which provides a plurality of functional blocks utilize the shadow register in a mutually time-exclusive manner.

Abstract: A programmable disk array controller distributes contiguous data from a host processor across a plurality of disk drives. The controller includes a device port with a plurality of connected disk drives. A dual ported buffer memory receives data from the host processor for storage to the disk drives. The programmable controller accesses data from the buffer memory and causes it to be fed to the device port for storage in the disk drives. The programmable controller includes a variable increment counter associated with each disk drive for controlling the data address accessed from the buffer memory. Each variable increment counter is programmable to sequentially increment a count by a value n so that its associated disk drive receives every nth data segment from the buffer memory.