Abstract: A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a non-linear function to produce training .phi. vectors. A systolic array arranged for QR decomposition and least means squares processing forms combinations of the elements of each .phi. vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed test data to provide estimates of unknown results. The processor is applicable to provide estimated results for problems which are non-linear and for which explicit mathematical formalisms are unknown.

Abstract: A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a nonlinear function to produce training .phi. vectors. A systolic array arranged for QR decomposition and least mean squares processing forms combinations of the elements of each .phi. vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed test data to provide estimates of unknown results. The processor is applicable to provide estimated results for problems which are nonlinear and for which explicit mathematical formalisms are unknown.

Abstract: A processor suitable for recursive computations is arranged to multiply successive input data words by a co-efficient word to produce results. It incorporates multiplier cells connected to form rows and columns. Each row is arranged to multiply a respective input data digit by the co-efficient. It begins with accumulator cells and continues with multiplier cells each arranged to multiply by an individual co-efficient digit and disposed in the row in descending order of digit significance. Columns other than the first column begin with a multiplier cell, and the higher significance columns terminate at respective accumulator cells. Any intervening multiplier cells are arranged in ascending order of multiplier digit significance. The processor employs radix 2 arithmetic. Each accumulator cell employs redundant radix 2 arithmetic, and each adds the highest significance transfer digit output of its row to at least three digits of equal and higher significance output from a preceding row.

Abstract: A digital processor for two's complement computations incorporates an array of multiplier cells each having the one-bit gated full adder logic function. The array has nearest-neighbour connections containing clock-activated latches for bit propagation. On each clock cycle, the cells receive input data, carry and cumulative sum bits. Each cell adds the carry and cumulative sum bits to the product of the data bit and a respective digit associated with the relevant cell. Data bits pass along array rows and sum bits accumulate in cascade down array columns. Carry bits are recirculated. Each coefficient digit is expressed as a sign bit and at least one magnitude bit consisting of or including a level bit. Each cell includes logic gates responsive to the sign and level bits, and carry a feedback latch and multiplier combination responsive to a least significant data bit flag to substitute the sign bit for a carry feedback bit.

Abstract: A processor is provided which is suitable for constrained least squares computations. It incorporates a systolic array of boundary, internal, constraint and multiplier cells arranged as triangular and rectangular sub-arrays. The triangular sub-array contains boundary cells along its major diagonal and connected via delays, together with above-diagonal internal cells. It computes and updates a QR decomposition of a data matrix X incorporating successive data vectors having individual signals as elements. The rectangular sub-array incorporates constraint cell columns each implementing a respective constraint vector and terminating at a respective multiplier cell. The constraint cells store respective conjugate constraint factors obtained by constraint vector transformation in the triangular sub-array. Rotation parameters produced by QR decomposition in the triangular sub-array are employed by the rectangular sub-array to rotate a zero input and update stored constraint factors.

Abstract: A digital processor performs an N-point convolution or correlation of q-bit coefficients with data words guard band extended to p bits. The processor includes an array of one-bit clock-activated gated full adder cells arranged in N rows and q columns. Each cell is arranged to input data, carry and cumulative sum bits and to output the data bit and new carry and cumulative sum bits corresponding to the product of the input data bit with a respective stationary coefficient bit. The output carry bit is recirculated on the respective cell. Cumulative sum generation is cascaded down array columns. Data moves along each row and thence to the next lower row via a delay device providing a delay appropriate for correct partial product formation. Data is input bit and word serially to a first row cell and thereafter moves along successive rows progressively further down the array.

Abstract: A bit-slice digital processor for performing an N-point correlation or convolution of N single-bit coefficients with a bit parallel, word serial, bit-staggered stream of M bit data words. The processor includes an N row, M column array of one-bit gated full adders with rows extended by half adders to accommodate word growth. Intercell connections incorporating clock activated latches provide for data and result flow unidirectionally down columns, one at twice the rate of the other. Carries and coefficients move unidirectionally along array rows at the faster (data or result) rate. Complex computations are executed by arrays of processors each with output delaying means and an adder to sum separate processor contributions. The processor may include data and result bypass connections subdivided by clocked latches for bypassing without operating speed penalties, as required for fault-tolerant processor array construction.

Abstract: A systolic array of cells for processing a data stream includes an arrangement of nearest-neighbor connected boundary cells, internal cells and a multiplier, arranged as a triangular array and a column. The boundary cells are diagonally interconnected. Each boundary cell evaluates sine and cosine rotation parameters from data received from above for lateral transfer to a neighboring internal cell, and multiplies a diagonal input by the cosine parameter for diagonal output. Each internal cell receives rotation parameters from the left, applies them to data from above to produce an output below, and passes them on laterally. Data input to the column becomes cumulatively rotated before output from the final downstream internal cell. The final downstream boundary cell provides cumulatively multiplied cosine parameters. The multiplier provides the product of the outputs of these final cells. The product is the least squares residual arising from weighted minimization of input signals.

Abstract: A digital data processor is provided to multiply data elements by coefficients. It includes a systolic array of cells consisting of nearest neighbor connected gated full adders. The cells multiply data bits received from laterally adjacent cells and subsequently pass them on. The product is added to a cumulative sum bit from a cell above and to a carry bit recirculated from an earlier computation. The output is passed to a cell below, and a new carry bit is recirculated for addition in a subsequent computation. Data and coefficients are input in counterflow to opposite sides of the array. An adder tree accumulates non-simultaneously computed contributions to individual output terms. The tree incorporates a delay and switches arranged to implement or bypass the delay according to earlier or later computation of a contribution. By virtue of this accumulation, the processor provides reduced cell redundancy compared to the prior art.

Abstract: A constraint application processor is arranged to apply a linear constraint to signals from antennas. A main antenna signal is fed to constraint element multipliers and then to respective adders for subtraction from subsidiary antenna signals. Delay units delay the subsidiary signals by one clock cycle prior to subtraction. The main signal is also fed via a one cycle delay unit to a multiplier for amplification by a gain factor. Main and subsidiary outputs of the processor may be connected to an output processor for signal minimization subject to the main gain factor remaining constant. The output processor may be arranged to produce recursive signal residuals in accordance with the Widrow LMS (Least Mean Square) algorithm. This requires a processor arranged to sum main and weighted subsidiary signals, weight factors being derived from preceding data, residual and weight factors. Alternatively, a systolic array of processing cells may be employed.

Abstract: A digital data processor for matrix/matrix multiplication includes a systolic array of nearest neighbor connected gated full adders. The adders are arranged to multiply two input data bits and to add their product to an input cumulative sum bit and a carry bit from a lower order bit computation. The result and input data bits are output to respective neighboring cells, a new carry bit being recirculated for later addition to a higher order bit computation. Column elements of one matrix and row elements of the other are input to either side of the array bit-serially, least significant bit leading, for mutual counterpropagation therethrough with a cumulative time delay between input of adjacent columns or rows. Bit-level matrix interactions for product matrix computation occur at individual cells. Pairs of intercalated adder trees are connected switchably to the array to accumulate bit-level contributions to product matrix elements.

Abstract: The invention provides a digital data processor which has been systemetized down to bit level. The processor includes a regular array of identical processing cells which perform a logic operation on incoming bits. The cells repeatedly perform a cell operation under the control of clocks which govern the inputting to and outputting from the cell of data bits. Each bit takes part in a maximum of one cell operation in one repetition of the clock having the highest repetition frequency. Processing cell arrays for dealing with larger numbers may be readily built up from smaller arrays used for smaller numbers. Having obtained a fully working design for one type of processing cell, the full array consisting of a plurality of cells is proven.

Abstract: A digital signal processor has timing means for providing a succession of sample intervals in which incoming digital signals may have discrete values (e(o)). A serial delay such as a multi or single bit shift register progressively delays a digital signal giving a delayed signal (e(m)). An arithmetic section has a plurality of elements such as multi or single bit multipliers, or difference squares. Each element operates on non delayed signals (e(o)) and signals (e(m)) from an associated stage of the delay. An accumulating store has a plurality of channels each associated with and arithmetic element. Collectively the channels provide the required mathematical operation, e.g. auto or cross correlation function or structure function calculation. The interval of delay between channels is arranged to increase substantially geometrically e.g. by .sqroot.2. The overall delay increase may be variable and geometric although increases between adjacent channels may be approximations to a geometric increase.

Abstract: The invention provides a digital data processor which has been systemetized down to bit level. The processor includes a regular array of identical processing cells which perform a logic operation on incoming bits. The cells repeatedly perform a cell operation under the control of clocks which govern the inputting to and outputting from the cell of data bits. Each bit takes part in a maximum of one cell operation in one repetition of the clock having the highest repetition frequency.Processing cell arrays for dealing with larger numbers may be readily built up from smaller arrays used for smaller numbers.Having obtained a fully working design for one type of processing cell, the full array consisting of a plurality of cells is proven.