Abstract: An apparatus is described comprising a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input. Another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters where each inverter output is coupled to the next inverter input in the series. At least one of the inverters comprises a current source and a pair of transistors coupled to the current source.

Abstract: An apparatus is described comprising a noise source coupled to an input of a gain stage. The apparatus also includes a noise shaping stage that forms a shaped noise signal by reducing 1/f noise introduced by the gain stage. The noise shaping stage has an input coupled to an output of the gain stage. The apparatus also has a decision circuit that decides whether the shaped noise signal, or a signal derived from the shaped noise signal corresponds to a 1 or a 0. A method is described that amplifies a first noise signal to produce a second noise signal. A shaped noise signal is formed by reducing 1/f noise introduced to the second noise signal by the amplifying. A random sequence is generated by comparing, against a reference, the shaped noise signal or a signal derived from the shaped noise signal.

Abstract: A bubble suppression apparatus is disclosed comprising: a first set of AND gates, wherein each AND gate within the first set has an input configured to receive a binary thermometer code value and one or more adjacent binary thermometer code values; and a second set of AND gates, wherein each AND gate within the second set has an input coupled to two or more outputs of the first set of AND gates.

Abstract: A method is described that converts a first flow of data words into a second flow of data words. The first flow of data words has a first data rate and the second flow of data words has a second data rate. The second data rate is greater than the first data rate such that the second flow of data words under-runs. The method also includes transmitting the second flow of data words over a plurality of communication links. A data alignment data structure is transmitted over each of the communication links for each under-run.

Abstract: A DC coupled serial data stream receiver system utilizing a switched capacitor based differencing front end which compares the instantaneous value of an analog voltage with respect to its long term minimum value to a series of reference voltages V1 to Vn in a flash analog to digital converter style front end. The circuit is designed to interface directly to a discrete fiberoptic preamplifier. The receiver can handle multiple amplitude serial data as produced by multiple fiberoptic transmitters on the same fiber without any data loss and without any interruption in data transfer being necessary as one transmitter halts and a second one starts transmission.

Abstract: An apparatus having a white noise source which is coupled to a gain stage having an amplifier. The gain stage is coupled to a noise shaping stage which is also coupled to a decision circuit. Another apparatus having a white noise source which is differentially coupled to a gain stage that has a cascade of open loop amplifiers. The gain stage is differentially coupled to a noise shaping stage which is also differentially coupled to a decision circuit. A method that involves differentially coupling white noise into a gain stage. The white noise is differentially amplified with an amplifier which produces a first white noise signal. 1/f noise and offset voltage is substantially removed from said first white noise signal to produce a second white noise signal. A random sequence signal is produced by deciding whether the second white noise signal is a 1 or 0.

Abstract: A phase lock loop circuit for a digital radio generates the sampling frequency for sampling an incoming signal by storing the samples of the incoming signal in an accumulator at a first frequency. The accumulator is unloaded at the sampling frequency. A microprocessor monitors the rate in which the samples are stored in the accumulator and provides a switching signal to vary the sampling frequency in small increments to prevent the accumulator from overflowing or underflowing.

Abstract: The present invention is directed to various features of an implantable combined defibrillation/pacemaker system. The system's defibrillation delivery circuit provides for delivery of a multi-phase defibrillation waveform. It also includes features for insuring low patient current leakage. Protection circuitry is provided for protecting the pacing circuitry from damage by the high voltage defibrillation output. The dual channel cardiac pacing circuit accommodates bipolar and pseudo-unipolar pacing. The system includes the ability to detect defibrillator lead breaks without delivering a defibrillation pulse to the patient. An additional advantage of the disclosed system is its ability to use the pacing output stage for extremely high rate pacing to induce ventricular fibrillation.

Abstract: A low battery detect circuit shuts down high current circuitry in the system in the event that battery voltage drops to a level such that the regulated output voltage is endangered. The trigger voltage is dependent upon capacitor ratios and a reference voltage. The output of the detection circuitry is a digital signal which can be used to disable high current circuitry in an implantable medical device and, thus, allow the battery voltage to recover. Alternatively, the output of the detection circuitry can be used as a battery status indicator flag.

Abstract: A power supply down-conversion, regulation, and low battery detection system has application in an implantible defirillator but is also directly applicable to any battery powered implantible device. Battery voltage is down-converted by a high efficiency switched capacitor voltage divider to a suitable intermediate voltage. This voltage is then linearly regulated down to the desired output voltage. A second regulator, which takes current directly from the battery, supports the output voltage in the event that the load current cannot be supplied by the voltage downconverter. A low battery detect circuit shuts down high current circuitry in the system in the event that battery voltage drops to a level such that the regulated output voltage is endangered.

Abstract: A voltage measurement circuit is provided which can be used in a single supply situation, which has a measurement range from rail to rail and which uses a reference voltage which can lie anywhere between the rails but not at the rail to which measurements are to be referenced. The unknown voltage is sampled to a first plate of a capacitor. The second plate of the capacitor is connected to ground. The first plate of the capacitor is then connected to the first input of a comparator, the second input being connected to receive the reference voltage. If the unknown voltage is less than the reference voltage, the second plate of the capacitor is disconnected from ground and then connected to receive the reference voltage. Otherwise it remains connected to ground. The first plate of the capacitor is then connected to a constant current source, causing the voltage at the first comparator input to decrease linearly with time.