Abstract: A bus-to-bus interface circuit maps a portion of the address space of each bus to a corresponding portion of the address space of the other bus. When a computer processor one one bus attempts to read or write access a mapped address, the bus interface circuit obtains control of the other bus and read or write accesses a corresponding address on the other bus. The interface circuit permits a bus master on the first bus to lock both buses so that it may perform several bus-to-bus data read or write operations without having to re-arbitrate for control of either bus after each operation.

Abstract: An interface circuit permits a first bus master connected to a first bus to directly access a main memory connected to a second bus while maintaining coherency between corresponding data in the main memory and a cache memory used by a second bus master on the second bus. The interface circuit maps selected first bus addresses to corresponding second bus addresses such that when a bus master on the first bus attempts to read or write access one of the mapped first bus addresses, the bus interface circuit responds by read or write accessing a corresponding address in the memory on the second bus.

Abstract: An interface circuit board connected to a VMEbus standard backplane bus of a first data processing system, and also to a Futurebus standard backplane bus of a second data processing system, provides address/data conversion and interrupt service between the two standard bus structures. The Futurebus, being a higher level bus than the VMEbus, has no provision for hardware interrupts; event related data are conventionally transmitted across the Futurebus like any other data item. The interface board signals VMEbus interrupts to Futurebus devices by way of the Futurebus bus arbitration facility. Interrupts generated on the interface circuit board and interrupts from the VMEbus priority interrupt bus are mapped and converted into message numbers, one of which is asserted on the Futurebus arbitration bus as an arbitration number higher than the arbitration numbers assigned to Futurebus devices.

Abstract: A circuit board configuration for I/O devices and logic devices, wherein the I/O devices have current levels substantially higher than the current levels associated with the logic devices. The I/O devices are grouped adjacent a connector, and a ground return plane surrounds the I/O devices coupling the ground terminals of the I/O devices to the ground pins of the connector. The logic devices are spaced some distance away from the connector where the ground terminals of the logic devices are connected through vias to a ground plane. The ground return plane, forming a strip line with the ground, plane, is effective for isolating the I/O devices and reducing signal distortion on the board.

Abstract: An interface circuit in a modular electronic system includes duplex control-signal transmission lines. Modules connectable to a controller unit of the system transmit configuration data items by way of the duplex lines to the controller during a first time period, and the controller during a second time period generates module control signals in accordance with the configuration of the modules. The module control signals are transmitted to the modules on the duplex transmission lines.

Abstract: A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices. Each arbitration logic unit receives control signals by way of the unitary bus which are common to all the devices, each control signal being the logical OR of the corresponding signals from all other devices. The control signals include a device address/priority number and a synchronization signal set. The arbitration logic includes a priority resolver which awards bus access to a device having the highest address/priority number, and control logic which receives the common synchronization signal set and synchronizes the operation of the device in which the arbitration logic resides with all other devices contending for the unitary bus. The control logic and the priority resolver are programmable array logic circuits.

Abstract: A digital free-running clock oscillator comprises a circuit synchronizing the operation of the oscillator with an asynchronous timing signal from an external source, and is provided with a protection circuit for preventing a logic race condition in the synchronizing circuit during a period of coincident transition of the oscillator output and the external timing signal.

Abstract: A circuit is provided for encoding digital data to be recorded on high-density magnetic storage media. The circuit converts serial data to modified phase modulation encoded serial data with time encoding or write precompensation.

Abstract: A circuit is provided for encoding digital data to be recorded on high-density magnetic storage media. The circuit converts serial data to modified phase modulation encoded serial data with time encoding or write precompensation.

Abstract: A means and method for accessing a digital memory system in a manner permitting the transfer of a two-byte information signal into and out of a storage area defined by any two logically adjacent memory bytes. Provision is also made for maintaining a preselected locational integrity between the bytes forming the information signal.