Patents by Inventor John G. Torborg, Jr.

John G. Torborg, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6008820
    Abstract: A gsprite engine circuit reads a display list identifying gsprite image layers to be composited for display, retrieves gsprite image data from an external memory, and transforms the gsprite data to display device coordinates. The gsprite image layers represent independently rendered graphical objects in a graphics scene. The gsprite engine can simulate the motion of the graphical objects in a sequence of display images by performing affine transformations on the gsprite image layers. The interface to the gsprite engine circuit includes the display list and gsprite header blocks. The display list enumerates the gsprites to be composited as a display image. The header blocks describe a gsprite transform, which can be an affine transform, used to transform gsprites to display device coordinates. The header blocks also provide an array of references to image blocks or "chunks" comprising the gsprite.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: December 28, 1999
    Assignee: Microsoft Corporation
    Inventors: Joseph W. Chauvin, Steven A. Gabriel, Howard Good, Kent E. Griffin, William Chambers Powell, III, George Easton Scott, III, Michael A. Toelle, John G. Torborg, Jr., James E. Veres
  • Patent number: 5936616
    Abstract: A display controller, implemented in software or hardware, maintains the primary display image visible on a computer monitor in compressed subregions or chunks. The controller emulates a conventional frame buffer by making the compressed image appear as if it has a linear address space. Most of the image is compressed and the remainder is selectively decompressed and cached to satisfy read and write requests. To display the image, the controller decompresses the display image's constituent subregions and buffers the decompressed data so that it can be scanned out to a display monitor.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: August 10, 1999
    Assignee: Microsoft Corporation
    Inventors: John G. Torborg, Jr., James E. Veres, Om Kumar Sharma, George Easton Scott, III, William Chambers Powell, III
  • Patent number: 5886701
    Abstract: A graphics rendering chip serially renders a stream of geometric primitives to image regions called chunks. A set-up processor in the chip parses rendering commands and the stream of geometric primitives and computes edge equation parameters. A scan-convert processor receives the edge equation parameters from the set-up processor and scan converts the geometric primitives to produce pixel records and fragment records. An internal, double-buffered pixel buffer stores pixel records for fully covered pixel addresses and also stores references to fragment lists stored in a fragment buffer. A pixel engine performs hidden surface removal and controls storage of pixel and fragment records to the pixel and fragment buffers, respectively. An anti-aliasing engine resolves pixel data for one pixel buffer while the pixel engine fills the other pixel buffer with pixel data for the next chunk.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: March 23, 1999
    Assignee: Microsoft Corporation
    Inventors: Joseph W. Chauvin, Steven A. Gabriel, Howard Good, Kent E. Griffin, Mark L. Kenworthy, William Chambers Powell, III, George Easton Scott, III, Michael A. Toelle, John G. Torborg, Jr., James E. Veres
  • Patent number: 5864342
    Abstract: A method for rendering graphical objects in a scene to generate a display images includes dividing the geometric primitives of models in a scene among portions or "chunks" of the view space to which the primitives will be rendered, and then rendering geometry referenced to the chunks in series in a common depth buffer. Geometry for a chunk can be rendered, including sophisticated anti-aliasing and translucency computations, using a minimum of memory. Serially rendering object geometry in chunks provides an effective form of compression because pixel fragments can be generated for one chunk at a time and then resolved. Pixel fragments can be resolved in a post-processing step for one chunk while primitives for another chunk are rasterized.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: January 26, 1999
    Assignee: Microsoft Corporation
    Inventors: James T. Kajiya, John G. Torborg, Jr., Michael A. Toelle, Kent E. Griffin, Mark L. Kenworthy, John M. Snyder, Conal M. Elliott
  • Patent number: 5010515
    Abstract: An interactive 3-dimensional computer graphics display system has an arbitrary number of parallel connected graphic arithmetic processors (GAPS) coupled to an applications processor through a display list management module and coupled to an image memory unit that generates video output. High level commands from the applications processor are distributed for substantially equal temporal processing among the GAPS by delivering the commands to that GAP which is most ready to receive the next command. Each GAP has a FIFO input memory. A plurality of priority levels are established related to GAP FIFO input emptiness. An additional priority scheme is established within each FIFO emptiness level using a daisy-chained grant signal. A command bus includes dedicated lines for control signals between the GAPs to signal the priority and to pass along the grant signal.
    Type: Grant
    Filed: September 11, 1990
    Date of Patent: April 23, 1991
    Assignee: Raster Technologies, Inc.
    Inventor: John G. Torborg, Jr.
  • Patent number: 4970499
    Abstract: Disclosed is a three-dimensional display system that utilizes a host processor for performing geometric transformations and a local display processor for processing the user-supplied information which defines the object to be displayed. The display processor creates image data defining the location, color and intensity of each point of the overall image. This display processor processes and stores depth data which defines the corresponding depth relationships of the image points at each location of the overall image with the depth data being stored in a depth buffer, which is part of the display processor. The depth buffer is a two port memory device with one port being a random access port and the other being a serial access port. The display processor pieplines depth buffering operations by loading a row of data from the depth buffer into a shift register and then reading (a Read operation) the relevant pixel data through the serial access port which is connected to the shift register.
    Type: Grant
    Filed: July 21, 1988
    Date of Patent: November 13, 1990
    Assignee: Raster Technologies, Inc.
    Inventors: Eric L. Ryherd, Ross G. Werner, John G. Torborg, Jr.