Abstract: An expandable modular control system with reduced memory requirements comprising an electronic data processing (EDP) system employing a microprocessor device and having gated program interrupt means. In particular, the expandable modular control system of the present invention comprises a "universal" microprocessor module which can be selectively combined with other separately packaged peripheral support modules to implement any particular control system required. Control point modules comprising a matrix array of flip-flops arranged as a plurality of n-bit words and subject to program control serve as extensions of the memory module to control the states of corresponding points in the system under the control of the modular control system. Sense point modules similarly organized in a matrix array monitor or sense the status of the points in the system under control and provide input data to the microprocessor module.

Abstract: Apparatus for selecting the operational mode of a particular input/output device in an expandable modular electronic data processing system employing microprocessor devices and testing the I/O device without the use of additional input/output addresses. Input/output interface modules associated with corresponding ones of the I/O devices include a plurality of flip-flops having corresponding memory addresses associated therewith for testing and selecting the operational mode of the I/O device in accordance with the contents of the flip-flops.

Abstract: A bus assigner in an electronic data processing system for selectively assigning access to a system bus to one of a plurality of microprocessors comprising a multiprocessing system. In an embodiment of the present invention, logic circuitry is provided for assigning a priority of operation to each of the microprocessors, each microprocessor having a different assigned priority. The bus assigner selectively assigns access to the sysstem bus to the microprocessor having the highest priority whenever one or more of the microprocessors requests access to the system bus. In an alternative embodiment, the bus assigner sequentially scans the microprocessors for requests for access to the system bus and assigns access to the system bus in the order in which the requests are received by the bus assigner as it scans the microprocessors.