Patents by Inventor John Garney

John Garney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10885202
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Francis X. McKeen, Carlos V. Rozas, Uday R. Savagaonkar, Simon P. Johnson, Vincent Scarlata, Michael A. Goldsmith, Ernie Brickell, Jiang Tao Li, Howard C. Herbert, Prashant Dewan, Stephen J. Tolopka, Gilbert Neiger, David Durham, Gary Graunke, Bernard Lint, Don A. Van Dyke, Joseph Cihula, Stalinselvaraj Jeyasingh, Stephen R. Van Doren, Dion Rodgers, John Garney, Asher Altman
  • Publication number: 20190087586
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 21, 2019
    Inventors: Francis X. McKEEN, Carlos V. ROZAS, Uday R. SAVAGAONKAR, Simon P. JOHNSON, Vincent SCARLATA, Michael A. GOLDSMITH, Ernie BRICKELL, Jiang Tao LI, Howard C. HERBERT, Prashant DEWAN, Stephen J. TOLOPKA, Gilbert NEIGER, David DURHAM, Gary GRAUNKE, Bernard LINT, Don A. VAN DYKE, Joseph CIHULA, Stalinselvaraj JEYASINGH, Stephen R. VAN DOREN, Dion RODGERS, John GARNEY, Asher ALTMAN
  • Patent number: 10102380
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Francis X. McKeen, Carlos V. Rozas, Uday R. Savagaonkar, Simon P. Johnson, Vincent Scarlata, Michael A. Goldsmith, Ernie Brickell, Jiang Tao Li, Howard C. Herbert, Prashant Dewan, Stephen J. Tolopka, Gilbert Neiger, David Durham, Gary Graunke, Bernard Lint, Don A. Van Dyke, Joseph Cihula, Stalinselvaraj Jeyasingh, Stephen R. Van Doren, Dion Rodgers, John Garney, Asher Altman
  • Patent number: 9087200
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: July 21, 2015
    Assignee: Intel Corporation
    Inventors: Francis X. McKeen, Carlos V. Rozas, Uday R. Savagaonkar, Simon P. Johnson, Vincent Scarlata, Michael A. Goldsmith, Ernie Brickell, Jiang Tao Li, Howard C. Herbert, Prashant Dewan, Stephen J. Tolopka, Gilbert Neiger, David Durham, Gary Graunke, Bernard Lint, Don A. Van Dyke, Joseph Cihula, Stalinselvaraj Jeyasingh, Stephen R. Van Doren, Dion Rodgers, John Garney, Asher Altman
  • Publication number: 20130198853
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Application
    Filed: March 13, 2013
    Publication date: August 1, 2013
    Inventors: Francis X. McKEEN, Carlos V. ROZAS, Uday R. SAVAGAONKAR, Simon P. JOHNSON, Vincent SCARLATA, Michael A. GOLDSMITH, Ernie BRICKELL, Jiang Tao LI, Howard C. HERBERT, Prashant DEWAN, Stephen J. TOLOPKA, Gilbert NEIGER, David DURHAM, Gary GRAUNKE, Bernard LINT, Don A. VAN DYKE, Joseph CIHULA, Stalinselvaraj JEYASINGH, Stephen R. VAN DOREN, Dion RODGERS, John GARNEY, Asher ALTMAN
  • Publication number: 20130159726
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Application
    Filed: June 19, 2012
    Publication date: June 20, 2013
    Inventors: Francis X. MCKEEN, Carlos V. Rozas, Uday R. Savagaonkar, Simon P. Johnson, Vincent Scarlata, Michael A. Goldsmith, Ernie Brickell, Jiang Tao Li, Howard C. Herbert, Prashant Dewan, Stephen J. Tolopka, Gilbert Neiger, David Durham, Gary Graunke, Bernard Lint, Don A. Van Dyke, Joseph Cihula, Stalinselvaraj Jeyasingh, Stephen R. Van Doren, Dion Rodgers, John Garney, Asher Altman
  • Patent number: 7640426
    Abstract: Methods and apparatus are disclosed to boot a basic input/output system (BIOS) for a partitioned platform. An example method disclosed herein identifies at least one hardware component unique to a partition, determines which hardware components have commonality with the partition, initializes the at least one hardware component having commonality, and initializes the at least one hardware component unique to the partition. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: December 29, 2009
    Assignee: Intel Corporation
    Inventor: John Garney
  • Publication number: 20070234031
    Abstract: Methods and apparatus are disclosed to boot a basic input/output system (BIOS) for a partitioned platform. An example method disclosed herein identifies at least one hardware component unique to a partition, determines which hardware components have commonality with the partition, initializes the at least one hardware component having commonality, and initializes the at least one hardware component unique to the partition. Other embodiments are described and claimed.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventor: John Garney
  • Patent number: 7260672
    Abstract: A destructive-read memory is one that the process of reading the memory causes the contents of the memory to be destroyed. Such a memory may be used in devices that are intended to acquire data that may have associated usage restrictions, such as an expiration date, usage count limit, or data access fee for the acquired data. Typically, to enforce usage restrictions, and protect against theft, complex and often costly security techniques are applied to acquired data. With destructive-read memory, complex and costly security is not required for stored data. In one embodiment, a write-back mechanism, which may employ security, is responsible for enforcing usage restrictions. If the write-back mechanism determines continued access to acquired data is allowed, then it writes back the data as it is destructively read from the memory.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: August 21, 2007
    Assignee: Intel Corporation
    Inventor: John Garney
  • Publication number: 20070192537
    Abstract: A method and apparatus for preserving the processing order of some requests in a system is disclosed. The method may include blocking requests from executing based on a blocked count data field, blocking list data field, and a last request data field. The apparatus may include a system or a memory device.
    Type: Application
    Filed: April 20, 2007
    Publication date: August 16, 2007
    Inventors: John Garney, Robert Royer, Michael Eschmann, Daniel Nemiroff
  • Publication number: 20070136550
    Abstract: A method includes establishing two partitions, including a first partition and a second partition, in a computer system. The method further includes designating a first memory page in memory space controlled by the first partition, designating a second memory page in memory space controlled by the second partition, storing an address of the first memory page in an address mapping array that is accessible by the first partition and storing an address of the second memory page in an address mapping array that is accessible by the second partition. In addition, the method includes exchanging the address of the first memory page in the address mapping array that is accessible by the first partition with the address of the second memory page in the address mapping array that is accessible by the second partition.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 14, 2007
    Inventor: John Garney
  • Publication number: 20070088884
    Abstract: A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.
    Type: Application
    Filed: November 13, 2006
    Publication date: April 19, 2007
    Applicant: INTEL CORPORATION
    Inventors: John Garney, Robert Royer
  • Patent number: 7174285
    Abstract: This invention relates to a method and apparatus for assessing quality of service for communication networks. More particularly, the invention is directed to assessing quality of service in circuit and packet switched networks by way of a computer simulation. Preferably, the information necessary to conduct the assessment activity is available via the internet from a web server that also compiles statistical data on the resultant quality of service assessments.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: February 6, 2007
    Assignee: Lucent Technologies Inc.
    Inventor: David John Garney
  • Publication number: 20070005881
    Abstract: In some embodiments, a method to minimize memory bandwidth usage in optimal disk transfers is presented. In this regard, a transfer agent is introduced to read a plurality of contiguous sections of a mass storage device in a single operation, and to transfer data from fewer than all the sections read. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventor: John Garney
  • Publication number: 20060294339
    Abstract: Embodiments of abstracted dynamic addressing are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Sanjeev Trika, Robert Royer, John Garney, Richard Mangold
  • Publication number: 20060215437
    Abstract: Memory cells, such as polymer memory cells, that are prone to imprinting, may be refreshed. In addition, if despite periodic refreshing, the cells become imprinted anyway, this may be detected and counter measures taken to prevent adverse consequences.
    Type: Application
    Filed: March 28, 2005
    Publication date: September 28, 2006
    Inventors: Sanjeev Trika, John Garney, Robert Royer
  • Publication number: 20060129763
    Abstract: Processor-based systems may include a disk cache to increase system performance in a system that includes a processor and a disk drive. The disk cache may include physical cache lines and virtual cache lines to improve cache insertion and eviction policies. The virtual cache lines may also be useful when recovering from failed requests.
    Type: Application
    Filed: February 10, 2006
    Publication date: June 15, 2006
    Inventors: Robert Royer, Sanjeev Trika, Jeanna Matthews, John Garney, Michael Eschmann
  • Publication number: 20060036806
    Abstract: A disk cache may include a volatile memory such as a dynamic random access memory and a nonvolatile memory such as a polymer memory. When a cache line needs to be allocated on a write, the polymer memory may be allocated and when a cache line needs to be allocated on a read, the volatile memory may be allocated.
    Type: Application
    Filed: October 17, 2005
    Publication date: February 16, 2006
    Inventor: John Garney
  • Publication number: 20050278486
    Abstract: In one embodiment, the present invention includes a method for writing data to a disk if inserting the data into a cache, such as a disk cache associated with the disk, would cause a threshold of dirty data in the cache to be met or exceeded. Further, in certain embodiments, the cache may store data according to a first cache policy and a second cache policy. A determination of whether to store data according to the first or second policies may be dependent upon an amount of dirty data in the cache, in certain embodiments. In certain embodiments, the cache may include at least one portion reserved for clean data.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 15, 2005
    Inventors: Sanjeev Trika, John Garney, Michael Eschmann
  • Publication number: 20050251630
    Abstract: In one embodiment of the present invention, a method may include determining whether requested information is part of a streaming access, and directly writing the requested information from a storage device to a memory if the requested information is part of the streaming access. Alternately, if the requested information is not part of the streaming access, it may be written from the storage device to a cache. In various embodiments, the cache may be a non-volatile disk cache.
    Type: Application
    Filed: May 4, 2004
    Publication date: November 10, 2005
    Inventors: Jeanna Matthews, John Garney