Patents by Inventor John Gatt

John Gatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of generating a restricted inline resistive fault pattern and a test pattern generator
    Patent number: 8055467
    Abstract: A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: November 8, 2011
    Assignee: LSI Corporation
    Inventors: Jeff S. Brown, Marek Marasch, John Gatt
  • METHOD OF GENERATING A RESTRICTED INLINE RESISTIVE FAULT PATTERN AND A TEST PATTERN GENERATOR
    Publication number: 20100153056
    Abstract: A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Applicant: LSI Corporation
    Inventors: Jeff S. Brown, Marek Marasch, John Gatt