Abstract: A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Abstract: A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Abstract: A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. A charge pump system is coupled with the phase detector, including (1) a charge pump responsive to assertion of actuating signals from the UP output and the DOWN output to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust a bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Abstract: A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Abstract: A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Abstract: A phase-locked loop system and method are provided. The system may include an error detector configured to receive a reference signal, and a voltage-controlled oscillator subsystem coupled to the error detector. The voltage-controlled oscillator subsystem is typically configured to produce a primary output signal that tends toward a predefined frequency relationship with the reference signal, and to produce a feedback signal that is routed in a feedback loop back to the error detector. The voltage-controlled oscillator subsystem typically includes a multiple output voltage-controlled oscillator having a plurality of VCO outputs. The voltage-controlled oscillator subsystem is typically configured to form the feedback signal from a plurality of the VCO outputs.

Abstract: A phase-locked loop system configured to cause an output signal to tend toward a desired output frequency. The phase-locked loop system includes a charge pump system and an oscillator operatively coupled with the charge pump system. The charge pump system is configured to selectively effect proportional control over the output signal by producing a correcting pulse having a duration and applying the correcting pulse to a proportional control path of the phase-locked loop system. The charge pump system includes a correcting circuit configured to store a correcting charge corresponding to the correcting pulse, and then output the correcting charge over a period of time that is greater than the duration of the correcting pulse. Other configurations of the phase-locked loop system employ programmable current mirrors, and other structures and methods, to reduce charge pump current within the phase-locked loop.

Abstract: A phase-locked loop configured to cause an output signal to tend toward a desired output frequency based on an applied reference signal. In a first configuration, the phase-locked loop includes a voltage controlled oscillator operatively coupled with a bias generator. The voltage controlled oscillator is configured to produce the output signal in response to a VCO current generated via application of a biasing signal from the bias generator. The VCO current produces a regulated VCO voltage within the voltage controlled oscillator, and the bias generator is configured so that the regulated bias generator voltage matches the regulated VCO voltage free of any direct coupling between the bias generator and the regulated VCO voltage. In another configuration, the phase-locked loop includes a charge pump system having semiconductor components that correspond to only a portion of a voltage controlled oscillator associated with the loop.

Abstract: A programmable current mirror, including a reference system configured to receive a reference current, and a mirror system operatively connected to the reference system and configured to produce an output current based on the applied reference current. The relationship between the reference current and the mirror current is defined by a programmably variable mirroring parameter. The reference system includes a plurality of transistor groups, each transistor group being configured to alter the mirroring parameter via programmable variation of a dimensional parameter associated with the transistor group. Variations to the mirroring parameter produced by one of the transistor groups are scaled relative to variations produced by another of the transistor groups. The reference system, mirror system or both may be implemented with a multistage configuration. The current mirror may also be configured to provide inverse linear programmability.

Abstract: A phase-locked loop system and method are provided. The system may include an error detector configured to receive a reference signal, and a voltage-controlled oscillator subsystem coupled to the error detector. The voltage-controlled oscillator subsystem is typically configured to produce a primary output signal that tends toward a predefined frequency relationship with the reference signal, and to produce a feedback signal that is routed in a feedback loop back to the error detector. The voltage-controlled oscillator subsystem typically includes a multiple output voltage-controlled oscillator having a plurality of VCO outputs. The voltage-controlled oscillator subsystem is typically configured to form the feedback signal from a plurality of the VCO outputs.

Abstract: A programmable current mirror, including a reference system configured to receive a reference current, and a mirror system operatively connected to the reference system and configured to produce an output current based on the applied reference current. The relationship between the reference current and the mirror current is defined by a programmably variable mirroring parameter. The reference system includes a plurality of transistor groups, each transistor group being configured to alter the mirroring parameter via programmable variation of a dimensional parameter associated with the transistor group. Variations to the mirroring parameter produced by one of the transistor groups are scaled relative to variations produced by another of the transistor groups. The reference system, mirror system or both may be implemented with a multistage configuration. The current mirror may also be configured to provide inverse linear programmability.

Abstract: A phase-locked loop configured to cause an output signal to tend toward a desired output frequency based on an applied reference signal. In a first configuration, the phase-locked loop includes a voltage controlled oscillator operatively coupled with a bias generator. The voltage controlled oscillator is configured to produce the output signal in response to a VCO current generated via application of a biasing signal from the bias generator. The VCO current produces a regulated VCO voltage within the voltage controlled oscillator, and the bias generator is configured so that the regulated bias generator voltage matches the regulated VCO voltage free of any direct coupling between the bias generator and the regulated VCO voltage.

Abstract: A phase-locked loop system configured to cause an output signal to tend toward a desired output frequency. The phase-locked loop system includes a charge pump system and an oscillator operatively coupled with the charge pump system. The charge pump system is configured to selectively effect proportional control over the output signal by producing a correcting pulse having a duration and applying the correcting pulse to a proportional control path of the phase-locked loop system. The charge pump system includes a correcting circuit configured to store a correcting charge corresponding to the correcting pulse, and then output the correcting charge over a period of time that is greater than the duration of the correcting pulse.

Abstract: A system and method for using self-biased circuits to reduce phase jitter and phase offset in phase locked loops and frequency is disclosed. A self-biased apparatus for aligning a reference signal having reference phase with a feedback signal having a feedback phase includes a phase-frequency detector for comparing the reference phase and the feedback phase. The phase-frequency detector produces a phase-frequency detector output proportional to a difference between the reference phase and the feedback phase. A charge pump, coupled to the phase-frequency detector, outputs a charge pump output in response to the phase-frequency detector output. A loop filter, coupled to the charge pump, filters the charge pump output to produce a control voltage. A bias generator is coupled to the loop filter to generate a bias signal to bias the charge pump, causing the charge pump to generate a bias voltage substantially equivalent to the control voltage.

Abstract: An array oscillator circuit is disclosed herein. The array oscillator circuit includes a plurality of ring oscillators, each ring oscillator having a plurality of buffer stages for generating output signals on a like plurality of oscillator output ports. Interconnections are provided between each of the plurality of ring oscillators and at least one other of the plurality of ring oscillators such that the plurality of ring oscillators oscillate at identical frequencies and such that the output signals on the each ring oscillator's plurality of oscillator output ports have a phase offset from the signals generated on corresponding ones of the other ring oscillator's oscillator output ports. A multiplexer provides an electrical connection to a selected one of the plurality of oscillator output ports of the plurality of ring oscillators.