Patents by Inventor John Gierach
John Gierach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11688366Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.Type: GrantFiled: August 30, 2021Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
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Publication number: 20220414967Abstract: Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Prasoonkumar Surti, Jorge Garcia Pabon, John Gierach
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Publication number: 20220059054Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.Type: ApplicationFiled: August 30, 2021Publication date: February 24, 2022Applicant: Intel CorporationInventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
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Patent number: 11257182Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.Type: GrantFiled: July 30, 2020Date of Patent: February 22, 2022Assignee: INTEL CORPORATIONInventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
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Patent number: 11107444Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.Type: GrantFiled: December 20, 2019Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
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Patent number: 10937126Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.Type: GrantFiled: May 17, 2018Date of Patent: March 2, 2021Assignee: INTEL CORPORATIONInventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
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Publication number: 20210012452Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.Type: ApplicationFiled: July 30, 2020Publication date: January 14, 2021Applicant: Intel CorporationInventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
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Patent number: 10853989Abstract: Embodiments described herein provide an apparatus comprising a processor to maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse selection dispatch rate, receive a request message to dispatch coarse compute shader work, the request message comprising a requested coarse selection dispatch rate and a thread identifier, and store the request message in a FIFO queue structure having a coarse selection dispatch rate corresponding to the requested coarse selection dispatch rate associated with the request message. Other embodiments may be described and claimed.Type: GrantFiled: September 26, 2018Date of Patent: December 1, 2020Assignee: INTEL CORPORATIONInventor: John Gierach
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Patent number: 10839597Abstract: Apparatus and method for a multi-frequency vertex shader. For example, one embodiment of a graphics processing apparatus comprises a plurality of vertex caches to store vertex data associated with graphics primitives; and graphics execution circuitry to execute vertex shaders operable at different processing rates for different sets of the vertex data, each of the different sets of vertex data to having a different type of identifier associated therewith to identify the vertex data.Type: GrantFiled: August 28, 2018Date of Patent: November 17, 2020Assignee: Intel CorporationInventors: John Gierach, Daniel Walsh, John Feit, Devan Burke
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Patent number: 10748323Abstract: Embodiments described herein provide a general purpose graphics processing device, comprising a general purpose graphics processing compute block to process a workload including graphics or compute operations, a memory, and a constant folding unit comprising a processing unit to receive a first input shader and metadata for the first input shader, receive a first constant buffer comprising runtime constants for the first input shader, and generate an improved shader from the first input shader and the runtime constants. Other embodiments may be described and claimed.Type: GrantFiled: December 4, 2018Date of Patent: August 18, 2020Assignee: INTEL CORPORATIONInventors: John Gierach, Srividya Karumuri, Thomas Raoux, Devan Burke, Wojtek Rajski, Jeremy Brennan
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Patent number: 10733690Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.Type: GrantFiled: May 17, 2018Date of Patent: August 4, 2020Assignee: INTEL CORPORATIONInventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
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Publication number: 20200211511Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.Type: ApplicationFiled: December 20, 2019Publication date: July 2, 2020Inventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
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Publication number: 20200175741Abstract: Embodiments described herein provide a general purpose graphics processing device, comprising a general purpose graphics processing compute block to process a workload including graphics or compute operations, a memory, and a constant folding unit comprising a processing unit to receive a first input shader and metadata for the first input shader, receive a first constant buffer comprising runtime constants for the first input shader, and generate an improved shader from the first input shader and the runtime constants. Other embodiments may be described and claimed.Type: ApplicationFiled: December 4, 2018Publication date: June 4, 2020Applicant: Intel CorporationInventors: JOHN GIERACH, SRIVIDYA A. KARUMURI, THOMAS RAOUX, DEVAN BURKE, WOJTEK RAJSKI, JEREMY BRENNAN
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Publication number: 20200098159Abstract: Embodiments described herein provide an apparatus comprising a processor to maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse selection dispatch rate, receive a request message to dispatch coarse compute shader work, the request message comprising a requested coarse selection dispatch rate and a thread identifier, and store the request message in a FIFO queue structure having a coarse selection dispatch rate corresponding to the requested coarse selection dispatch rate associated with the request message. Other embodiments may be described and claimed.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Applicant: Intel CorporationInventor: JOHN GIERACH
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Publication number: 20200074726Abstract: Apparatus and method for a multi-frequency vertex shader. For example, one embodiment of a graphics processing apparatus comprises a plurality of vertex caches to store vertex data associated with graphics primitives; and graphics execution circuitry to execute vertex shaders operable at different processing rates for different sets of the vertex data, each of the different sets of vertex data to having a different type of identifier associated therewith to identify the vertex data.Type: ApplicationFiled: August 28, 2018Publication date: March 5, 2020Inventors: JOHN GIERACH, DANIEL WALSH, JOHN FEIT, DEVAN BURKE
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Patent number: 10540260Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.Type: GrantFiled: February 23, 2018Date of Patent: January 21, 2020Assignee: INTEL CORPORATIONInventors: Travis Schluessler, Abhishek Venkatesh, Elmoustapha Ould-Ahmed-Vall, John Gierach, Tomer Bar On, Devan Burke
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Patent number: 10522113Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.Type: GrantFiled: December 29, 2017Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
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Publication number: 20190355084Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.Type: ApplicationFiled: May 17, 2018Publication date: November 21, 2019Applicant: Intel CorporationInventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
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Publication number: 20190355091Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.Type: ApplicationFiled: May 17, 2018Publication date: November 21, 2019Applicant: Intel CorporationInventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
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Publication number: 20190266069Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.Type: ApplicationFiled: February 23, 2018Publication date: August 29, 2019Applicant: Intel CorporationInventors: Travis Schluessler, Abhishek Venkatesh, Elmoustapha Ould-Ahmed-Vall, John Gierach, Tomer Bar On, Devan Burke