Patents by Inventor John Gierach

John Gierach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11688366
    Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
  • Publication number: 20220414967
    Abstract: Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Jorge Garcia Pabon, John Gierach
  • Publication number: 20220059054
    Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
    Type: Application
    Filed: August 30, 2021
    Publication date: February 24, 2022
    Applicant: Intel Corporation
    Inventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
  • Patent number: 11257182
    Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 22, 2022
    Assignee: INTEL CORPORATION
    Inventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
  • Patent number: 11107444
    Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
  • Patent number: 10937126
    Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: March 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
  • Publication number: 20210012452
    Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.
    Type: Application
    Filed: July 30, 2020
    Publication date: January 14, 2021
    Applicant: Intel Corporation
    Inventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
  • Patent number: 10853989
    Abstract: Embodiments described herein provide an apparatus comprising a processor to maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse selection dispatch rate, receive a request message to dispatch coarse compute shader work, the request message comprising a requested coarse selection dispatch rate and a thread identifier, and store the request message in a FIFO queue structure having a coarse selection dispatch rate corresponding to the requested coarse selection dispatch rate associated with the request message. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 1, 2020
    Assignee: INTEL CORPORATION
    Inventor: John Gierach
  • Patent number: 10839597
    Abstract: Apparatus and method for a multi-frequency vertex shader. For example, one embodiment of a graphics processing apparatus comprises a plurality of vertex caches to store vertex data associated with graphics primitives; and graphics execution circuitry to execute vertex shaders operable at different processing rates for different sets of the vertex data, each of the different sets of vertex data to having a different type of identifier associated therewith to identify the vertex data.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: John Gierach, Daniel Walsh, John Feit, Devan Burke
  • Patent number: 10748323
    Abstract: Embodiments described herein provide a general purpose graphics processing device, comprising a general purpose graphics processing compute block to process a workload including graphics or compute operations, a memory, and a constant folding unit comprising a processing unit to receive a first input shader and metadata for the first input shader, receive a first constant buffer comprising runtime constants for the first input shader, and generate an improved shader from the first input shader and the runtime constants. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: August 18, 2020
    Assignee: INTEL CORPORATION
    Inventors: John Gierach, Srividya Karumuri, Thomas Raoux, Devan Burke, Wojtek Rajski, Jeremy Brennan
  • Patent number: 10733690
    Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 4, 2020
    Assignee: INTEL CORPORATION
    Inventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
  • Publication number: 20200211511
    Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 2, 2020
    Inventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
  • Publication number: 20200175741
    Abstract: Embodiments described herein provide a general purpose graphics processing device, comprising a general purpose graphics processing compute block to process a workload including graphics or compute operations, a memory, and a constant folding unit comprising a processing unit to receive a first input shader and metadata for the first input shader, receive a first constant buffer comprising runtime constants for the first input shader, and generate an improved shader from the first input shader and the runtime constants. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 4, 2020
    Applicant: Intel Corporation
    Inventors: JOHN GIERACH, SRIVIDYA A. KARUMURI, THOMAS RAOUX, DEVAN BURKE, WOJTEK RAJSKI, JEREMY BRENNAN
  • Publication number: 20200098159
    Abstract: Embodiments described herein provide an apparatus comprising a processor to maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse selection dispatch rate, receive a request message to dispatch coarse compute shader work, the request message comprising a requested coarse selection dispatch rate and a thread identifier, and store the request message in a FIFO queue structure having a coarse selection dispatch rate corresponding to the requested coarse selection dispatch rate associated with the request message. Other embodiments may be described and claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventor: JOHN GIERACH
  • Publication number: 20200074726
    Abstract: Apparatus and method for a multi-frequency vertex shader. For example, one embodiment of a graphics processing apparatus comprises a plurality of vertex caches to store vertex data associated with graphics primitives; and graphics execution circuitry to execute vertex shaders operable at different processing rates for different sets of the vertex data, each of the different sets of vertex data to having a different type of identifier associated therewith to identify the vertex data.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 5, 2020
    Inventors: JOHN GIERACH, DANIEL WALSH, JOHN FEIT, DEVAN BURKE
  • Patent number: 10540260
    Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: January 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Travis Schluessler, Abhishek Venkatesh, Elmoustapha Ould-Ahmed-Vall, John Gierach, Tomer Bar On, Devan Burke
  • Patent number: 10522113
    Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
  • Publication number: 20190355084
    Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Applicant: Intel Corporation
    Inventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
  • Publication number: 20190355091
    Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Applicant: Intel Corporation
    Inventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
  • Publication number: 20190266069
    Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Applicant: Intel Corporation
    Inventors: Travis Schluessler, Abhishek Venkatesh, Elmoustapha Ould-Ahmed-Vall, John Gierach, Tomer Bar On, Devan Burke