Abstract: An n-bit serial shift register in an ink jet print head operates in a print mode or a test mode. When the shift register is operating in the print mode, n bits of print data are serially scanned into n number of bit registers and are then latched out to heater addressing logic circuitry in the print head to control a print operation. When the circuit is operating in the test mode, x bits of test point data from x number of test nodes in the print head are loaded in parallel into x number of the n number of bit registers, and are then serially scanned out to a test data output. In this manner, a single shift register may be used to scan in print data and scan out test data, thereby providing observability and controllability of the internal logic nodes of the print head while minimizing logic size and the number of input/output connections on the print head.

Abstract: An apparatus provides identification information related to at least one ink jet print head in an ink jet printer. The apparatus includes a printer controller for providing a first identification data string comprising n number of bits, at least one of which has a first state, and no more than n−1 number of which have a second state different from the first state. Coupled to the printer controller is a first ink jet print head having a first serial input shift register. The first serial input shift register has at least n number of bit positions for receiving the n number of bits of the first identification data string. The first ink jet print head also includes at least n number of first latches, each of which is coupled to a corresponding one of the n number of bit positions of the first shift register. The n number of first latches are for latching the n number of bits of the first identification data string from the n number of bit positions of the first shift register.

Abstract: A print data loading circuit receives N bits of serial data on a serial input data line, and provides the input data to a data bus in an addressing circuit for addressing one or more image-forming elements in a printing device. The data loading circuit includes an N-bit serial shift register having N number of serially-coupled single-bit storage registers. The data loading circuit also includes N−1 number of data latches, each having a data input coupled to a data output of a corresponding one of the single-bit storage registers. The data outputs of the data latches are coupled to N−1 number of selection lines that are coupled to the data bus. Each data latch has a clock input that is coupled to the data output of the Nth storage register. Based on this configuration, a bit provided at the Nth-register data output acts as a load trigger bit to cause the other data bits in the other single-bit storage registers to be loaded into the N−1 number of data latches.

Abstract: A print data loading circuit receives N bits of serial data on a serial input data line, and provides the input data to a data bus in an addressing circuit for addressing one or more image-forming elements in a printing device. The data loading circuit includes an N-bit serial shift register having N number of serially-coupled single-bit storage registers. The data loading circuit also includes N−1 number of data latches, each having a data input coupled to a data output of a corresponding one of the single-bit storage registers. The data outputs of the data latches are coupled to N−1 number of selection lines that are coupled to the data bus. Each data latch has a clock input that is coupled to the data output of the Nth storage register. Based on this configuration, a bit provided at the Nth-register data output acts as a load trigger bit to cause the other data bits in the other single-bit storage registers to be loaded into the N−1 number of data latches.