Patents by Inventor John Gorman
John Gorman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250223055Abstract: A satellite may include an optical component, and an optical adjustment device coupled to the optical component. The optical adjustment device may include a base, and an adjustment flexure carried by the base. The adjustment flexure may be moveable between an unflexed neutral position and a flexed first position, and between the unflexed neutral position and a flexed second position. The optical adjustment device may further include a rotatable drive shaft carried by the base, a drive cam carried by the rotatable drive shaft, a first cam follower and a second cam follower. The cam may cause the first and second cam followers to selectively move the adjustment flexure between the unflexed neutral position and the flexed first flexed position or the second flexed position.Type: ApplicationFiled: January 9, 2024Publication date: July 10, 2025Inventors: Aidan BRAWLEY, Samuel HAN, Ethan HUFFMAN, Daniel DeSANTIS, Alan AKERSTROM, James GUREGIAN, Damien MADDEN, John GORMAN
-
Patent number: 11626161Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.Type: GrantFiled: July 6, 2021Date of Patent: April 11, 2023Assignee: Intel CorporationInventors: Davide Mantegazza, Kyung Jean Yoon, John Gorman, Dany-Sebastien Ly-Gagnon
-
Publication number: 20220254999Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features.Type: ApplicationFiled: February 28, 2022Publication date: August 11, 2022Inventors: Srivatsan VENKATESAN, Davide MANTEGAZZA, John GORMAN, Iniyan Soundappa ELANGO, Davide FUGAZZA, Andrea REDAELLI, Fabio PELLIZZER
-
Patent number: 11264567Abstract: Various embodiments of a three-dimensional cross-point (3D X-point) memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.Type: GrantFiled: November 19, 2019Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Srivatsan Venkatesan, Davide Mantegazza, John Gorman, Iniyan Soundappa Elango, Davide Fugazza, Andrea Redaelli, Fabio Pellizzer
-
Publication number: 20210335419Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Inventors: Davide MANTEGAZZA, Kyung Jean YOON, John GORMAN, Dany-Sebastien LY-GAGNON
-
Patent number: 11100987Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.Type: GrantFiled: March 26, 2020Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Kyung Jean Yoon, John Gorman, Dany-Sebastien Ly-Gagnon
-
Publication number: 20210151672Abstract: A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features.Type: ApplicationFiled: November 19, 2019Publication date: May 20, 2021Applicant: INTEL CORPORATIONInventors: SRIVATSAN VENKATESAN, DAVIDE MANTEGAZZA, JOHN GORMAN, INIYAN SOUNDAPPA ELANGO, DAVIDE FUGAZZA, ANDREA REDAELLI, FABIO PELLIZZER
-
Patent number: 10438659Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.Type: GrantFiled: July 17, 2018Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
-
Publication number: 20190013071Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.Type: ApplicationFiled: July 17, 2018Publication date: January 10, 2019Applicant: Intel CorporationInventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
-
Patent number: 10032508Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.Type: GrantFiled: December 30, 2016Date of Patent: July 24, 2018Assignee: Intel CorporationInventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
-
Publication number: 20180190353Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Applicant: Intel CorporationInventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
-
Patent number: 9580679Abstract: Disclosed herein are methods and systems for use in preparing a sample. The methods and systems may be used for lysing one or more structures in a sample (e.g., cells, viral particles, etc.). The methods and compositions may comprise a microfluidic chip or use thereof. The microfluidic chips disclosed herein may comprise (a) a substrate comprising a chamber, wherein at least one mechanical element may be located within the chamber; (b) a thermal element in contact with the chamber; and (c) at least one aperture within the surface of the substrate, wherein the aperture may be configured to insulate the chamber.Type: GrantFiled: September 20, 2013Date of Patent: February 28, 2017Assignee: California Institute of TechnologyInventors: Samuel Njoroge, John Gorman, George Maltezos, Axel Scherer
-
Patent number: 9166071Abstract: A polarization resistant solar cell using an oxygen-rich interface layer is provided. The oxygen-rich interface layer may be comprised of SiOxNy, which may have a graded profile that varies between oxygen-rich proximate to the solar cell to nitrogen-rich distal to the solar cell. A silicon oxide passivation layer may be interposed between the solar cell and the SiOxNy graded dielectric layer. The graded SiOxNy dielectric layer may be replaced with a non-graded SiOxNy dielectric layer and a SiN AR coating.Type: GrantFiled: December 24, 2009Date of Patent: October 20, 2015Assignee: Silicor Materials Inc.Inventors: Bill Phan, Renhua Zhang, John Gorman, Omar Sidelkheir, Jean Patrice Rakotoniaina, Alain Paul Blosse, Martin Kaes
-
Publication number: 20140087359Abstract: Disclosed herein are methods and systems for use in preparing a sample. The methods and systems may be used for lysing one or more structures in a sample (e.g., cells, viral particles, etc.). The methods and compositions may comprise a microfluidic chip or use thereof. The microfluidic chips disclosed herein may comprise (a) a substrate comprising a chamber, wherein at least one mechanical element may be located within the chamber; (b) a thermal element in contact with the chamber; and (c) at least one aperture within the surface of the substrate, wherein the aperture may be configured to insulate the chamber.Type: ApplicationFiled: September 20, 2013Publication date: March 27, 2014Applicant: California Institute of TechnologyInventors: Samuel NJOROGE, John GORMAN, George MALTEZOS, Axel SCHERER
-
Publication number: 20110094574Abstract: A polarization resistant solar cell is provided. The solar cell uses a dual layer dielectric stack disposed on the front surface of the cell. The dielectric stack consists of a passivation layer disposed directly on the front cell surface and comprised of either SiOx or SiON, and an outer AR coating comprised of SiCN.Type: ApplicationFiled: December 24, 2009Publication date: April 28, 2011Applicant: Calisolar Inc.Inventors: Renhua Zhang, Bill Phan, John Gorman, Alain Paul Blosse, Martin Kaes
-
Publication number: 20110094575Abstract: A polarization resistant solar cell using an oxygen-rich interface layer is provided. The oxygen-rich interface layer may be comprised of SiOxNy, which may have a graded profile that varies between oxygen-rich proximate to the solar cell to nitrogen-rich distal to the solar cell. A silicon oxide passivation layer may be interposed between the solar cell and the SiOxNy graded dielectric layer. The graded SiOxNy dielectric layer may be replaced with a non-graded SiOxNy dielectric layer and a SiN AR coating.Type: ApplicationFiled: December 24, 2009Publication date: April 28, 2011Applicant: Calisolar Inc.Inventors: Bill Phan, Renhua Zhang, John Gorman, Omar Sidelkheir, Jean Patrice Rakotoniaina, Alain Paul Blosse, Martin Kaes
-
Publication number: 20090151801Abstract: A method of operating a controller for a pool pump motor includes the steps of setting an operating mode for the pool pump motor, setting a torque value for the pool pump motor corresponding to the operating mode, setting a high operating threshold and a low operating threshold corresponding to the torque value, operating the pool pump motor in a constant torque mode using the torque value, monitoring an operating parameter of the pool pump motor corresponding to a load on the pool pump motor, discontinuing operating the pool pump motor when the operating parameter is higher than the high operating threshold or lower than the low operating threshold and signaling a pool pump motor fault upon the discontinuing operating the pool pump motor. The operating parameter of the pool pump motor is RPM or current supplied to the pool pump motor. Additionally disclosed are energy efficient pool hydraulic design techniques that increase the energy efficiency of hydraulic systems.Type: ApplicationFiled: December 12, 2008Publication date: June 18, 2009Inventors: John Gorman, William Lizalde, Robert Kulakowski
-
Publication number: 20070194976Abstract: A linear FM pulse radar with Doppler processing of co-polarized and cross-polarized radar return signals isolates the target echo signal content associated with a moving pedestrian to provide high quality target echo data for standoff HCE detection based on polarimetric signature analysis. Baseband co-polarized and cross-polarized radar return signals are repeatedly and coherently integrated across numerous successive radar return pulses to create co-polarized and cross-polarized range vs. velocity (Doppler) data maps. The co-polarized data map is used to identify a moving pedestrian, and co-polarized and cross-polarized data subsets corresponding to the identified pedestrian are extracted and subjected to polarization signature analysis to determine if the pedestrian is bearing explosive devices.Type: ApplicationFiled: February 17, 2006Publication date: August 23, 2007Inventors: John Reed, John Gorman
-
Publication number: 20070172899Abstract: Methods for separating, in a continuous, multizone fluid medium, cells, particles, or other molecules of interest (MOI) from associated or contaminating unwanted materials not of interest (MNOI). The invention involves forced movement of MOI into certain zones having properties which deter the entry of unwanted materials. Differential movement of MOI and MNOI occurs by active counterforces that move MNOI but not MOI. MOI are tagged with magnetic particles and moved with a magnetic field through a fluid, or zones, of higher specific gravity that prevents, by flotation counterforce, unwanted less dense materials from entering. Surfaces specifically coated with reactants are reactive with the MOI in the tagged magnetic particle complex and of buoyant or other forces are used to remove any unbound material from the surface before reading.Type: ApplicationFiled: March 8, 2007Publication date: July 26, 2007Inventors: Henry Graham, John Gorman, James Rowell
-
Patent number: D862271Type: GrantFiled: September 23, 2016Date of Patent: October 8, 2019Inventors: Paul A Guido, John Gorman