Abstract: A printed circuit board includes a power plane and a ground reference plane that includes two opposite sides. The power plane is positioned proximate one side of the ground reference plane. A signal layer is positioned proximate the other side of the ground reference plane to isolate the power plane from the signal layer. Any noise on the power plane or the signal layer is thus isolated by the intervening ground plane.

Abstract: A method and related configuration for attenuating high-frequency noise that may appear on power planes in printed circuit boards. In one embodiment, the noise attenuation means of the present invention involves applying a lower conductivity material between the conductive and dielectric layers within a printed circuit board. High-frequency noise is then attenuated by the skin effect. In another embodiment, the low conductivity material is applied between the power plane and dielectric layer within the printed circuit board. The low conductivity material may be a material, such as nickel or lead, having an electrical conductivity ranging between about 1×104 mhos/m and 5.8×107 mhos/m for layers having a thickness of about 2 mils.

Abstract: In a method of the present invention, performance characteristics of a printed circuit board are analyzed. The printed circuit board, bypass components and an applied stimulus are modeled. Each of the bypass components includes a capacitor and a resistor in series with each other. Alternatively, a second capacitor is coupled in parallel to the above capacitor and resistor. A simulation of the circuit model is then performed. In this embodiment of the invention, the simulation is responsive to the stimulus as is performed over a range of bypass resistor values. In another embodiment of the invention, a printed circuit board is described with components and characteristics that reduce noise. Such a printed circuit board includes a power plane and a plurality of bypass components. Moreover, the plurality of bypass components include bypass capacitors and bypass resistors coupled in series between the positive power plane and the negative power plane.

Abstract: A method and related configuration for attenuating high-frequency noise that may appear on power planes in printed circuit boards. In one embodiment, the noise attenuation means of the present invention involves applying a lower conductivity material between the conductive and dielectric layers within a printed circuit board. High-frequency noise is then attenuated by the skin effect. In another embodiment, the low conductivity material is applied between the power plane and dielectric layer within the printed circuit board. The low conductivity material may be a material, such as nickel or lead, having an electrical conductivity ranging between about 1×104 mhos/m and 5.8×107 mhos/m for layers having a thickness of about 2 mils.

Abstract: In a method of the present invention, performance characteristics of a printed circuit board are analyzed. The printed circuit board, bypass components and an applied stimulus are modeled. Each of the bypass components includes a capacitor and a resistor in series with each other. Alternatively, a second capacitor is coupled in parallel to the above capacitor and resistor. A simulation of the circuit model is then performed. In this embodiment of the invention, the simulation is responsive to the stimulus as is performed over a range of bypass resistor values. In another embodiment of the invention, a printed circuit board is described with components and characteristics that reduce noise. Such a printed circuit board includes a power plane and a plurality of bypass components. Moreover, the plurality of bypass components include bypass capacitors and bypass resistors coupled in series between the positive power plane and the negative power plane.

Abstract: A multi-user bus is divided into a number of bus portions, one for each user. Each bus portion is coupled, at one end, to one of the multiple users and through an impedance matching network to the other bus portions in a star configuration. The disclosed embodiment teaches various resistive impedance matching networks.

Abstract: A method for manufacturing a bus having enhanced signals qualities which includes the steps of determining the intrinsic inductance per unit length (L.sub.0) and intrinsic capacitance per unit length (C.sub.0) of the unloaded bus. The method also includes the step of determining the load capacitance per unit length (C.sub.d) of the bus that is attributable to the peripheral devices that will be attached to the bus. Based on these values, an adjustment inductance (L.sub.d) per unit length for the bus is calculated for the bus with L.sub.d being substantially equal to L.sub.0 * C.sub.d /C.sub.0. Finally, one inductor of value L.sub.d is added per unit length of the bus. The added adjustment inductance offsets the capacitance attributable to the peripheral devices attached to the bus. The result is that signals within the bus have rise and fall times acceptable for high speed operation.

Abstract: To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.

Abstract: A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.