Abstract: This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Violations of the ordering constraints result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.

Abstract: A virtual core management system including a first physical core and a second physical core, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a first temperature sensor configured to sense a temperature of the first physical core and a second temperature sensor configured to sense a temperature of the second physical core, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the temperature of the first physical core and the temperature of the second physical core.

Abstract: A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.

Abstract: A circuit for tracking memory operations with trace-based execution is disclosed. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Executing one of the active memory operations updates a checkpoint location. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. After the trace is committed, all of the checkpoint entries associated with the trace are invalidated.

Abstract: An instruction processing circuit includes a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a first type of sequence of operations, and a trace builder circuit operable to receive at least a portion of the sequence of operations of the first type and to generate, based thereon, a second type of sequence of operations, where the at least a portion of the sequence of operations of the first type represents a first portion of the sequence of instructions, where the first portion of the sequence of instructions includes at most one conditional control transfer instruction that, when present, ends the first portion of the sequence of instructions, and where the sequence of operations of the second type also represents the first portion of the sequence of instructions.

Abstract: A method and system of ensuring coherency of a sequence of instructions to be executed by a processor having a trace unit and an execution unit includes grouping at least a portion of the sequence of instructions to form at least one trace where a status of the at least one trace is set to a verified status when the at least one trace is formed; holding in the at least one trace a coherency component that includes a pointer to a physical address of the at least one trace; receiving, based on the coherency component, the pointer to the physical address as associated with an invalidating event, and in response thereto, setting the status of the at least one trace to be an unverified status; and preventing the at least one trace from being executed when the status of the at least one trace is the unverified status.

Abstract: A processor includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. The circuit also includes a sub-circuit that holds memory operation ordering information corresponding to the active memory operations. The sub-circuit detects violations of ordering constraints.

Abstract: An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Violations of the ordering constraints may be signaled too late to prevent an update of the cached data associated with the memory operations. A sub-circuit detects this condition and invalidates the checkpoint locations indicated by the checkpoint entries associated with the trace experiencing the violation and all younger traces.

Abstract: An instruction processing circuit for a processor is disclosed. The instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution unit of the processor. The instruction processing circuit comprises at least one cache circuit and the processing circuit includes a sequencer and a page translation buffer coupled to the sequencer for trace verification and maintaining coherency between a memory and the at least one cache.

Abstract: An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. When a memory operation attempts to update a cache line that may not be updated, the circuit attempts to upgrade the cache line. If this fails, a rollback request is generated that indicates the trace involved. The checkpoint locations associated with the indicated trace are overwritten along with those locations associated with all younger traces.

Abstract: An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution circuit of the processor. The instruction processing circuit includes a cache circuit operable to store a second type of sequence of operations that represents at least a portion of a first type of sequence of operations, where the sequence of operations of the second type includes at most one control transfer that, when present, ends a first portion of a sequence of instructions, where the cache circuit is further configured to store a third type of sequence of operations that represents a set of at least two sequences of operations.

Abstract: An instruction processing circuit includes a decoder circuit, a basic block builder circuit, a multi-block builder circuit, first and second predictor circuits, and a sequencer circuit, where the sequencer circuit is operable, in a first environment, to cause the first predictor circuit to generate a prediction for a particular conditional branch op concurrently with the second predictor circuit generating a prediction for another particular conditional branch op, where the sequencer circuit is also operable, in a second environment, to cause the first predictor circuit to generate a prediction for the particular conditional branch op sequentially with the second predictor circuit generating a prediction for the another particular conditional branch operation.

Abstract: An instruction processing circuit includes an instruction cache, a decoder configured to receive at least one of the instructions and to generate, based thereon, a decoder sequence of at least one operation. The circuit includes a basic block cache that includes a basic block sequence of at least one of the operations. The basic block sequence is derived from at least one of the decoder sequences and includes at most one conditional control transfer operation. The circuit includes a multi-block cache that includes a multi-block sequence consisting of at least one of the operations derived from two or more smaller op sequences. A sequencer is configured to generate a prediction for the result of a conditional control transfer operation, select the next sequence of operations, and provide an indication of the next sequence to the instructions cache, the basic block cache, and the multi-block cache.

Abstract: An instruction processing circuit for a processor includes a decoder circuit, a cache circuit, a sequencer circuit operable to select a next sequence of operations, and an operations fetch circuit operable to convey the next sequence of operations to an execution circuit, receive an indication that a sequencing action of the sequencer circuit is sequencing ahead of the execution circuit, and switch, based on the indication, a source of the operations fetch circuit between the cache circuit and the decoder circuit.

Abstract: An instruction processing unit includes a trace builder circuit operable to (i) receive at least a portion of a first type of sequence of operations and to generate, based thereon, a second type of sequence of operations, where the portion includes at most one control transfer instruction that, when present, ends the portion, (ii) receive sets of at least two sequences of operations and to generate, based thereon, a plurality of third type of sequences of operations, where a sequence of operations of the third type includes one or more interior control transfer instructions and is generated from the sequence of operations of the second type and another sequence of operations of the third type, and (iii) retrieve the sequence of operations of the second type and the another sequence of operations of the third type from a cache circuit.

Abstract: A method and system for promoting traces in an instruction processing circuit is disclosed. The method and system comprises determining if a current trace is promotable; and adding the current trace to a sequence buffer if the current trace is promotable. The current trace is marked as promoted and the current trace is marked as a first trace of a multi-block trace. The method and system includes determining if a next trace is promotable; adding the next trace to the sequence buffer if the next trace is promotable; and repeating the above until the next trace is not promotable and then adding the next trace to the sequence buffer if the next trace is not promotable.

Abstract: A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include associating a symbolic expression with each of at least a subset of the registers, holding a set of dependency indications that specify for each particular symbolic expression which, if any, of the other symbolic expressions must be emitted as operations prior to emitting the particular symbolic expression, locating an operation, if any, that is next within the sequence of operations and setting that operation to be a working operation and processing the working operation.

Abstract: This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. Traces execute atomically and become eligible for commitment after all the operations in the trace have executed. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Rollback requests result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.

Abstract: A method of determining a reason for a trace to be aborted includes receiving at least two incoming indications of occurrences of abort triggers stemming from the execution of at least two of the operations that are different from each other, where each of the abort triggers has an associated abort priority level, and where the trace represents multiple instructions. The method further includes prioritizing among the abort triggers for the trace based on the abort priority level of each abort trigger, where the prioritizing does not take into account a correspondence between operations and instructions and where the prioritizing selects as a pending abort reason one or more of the abort triggers that have the same abort priority level, and where that abort priority level is the highest among the abort priority levels of the abort triggers for the trace.

Abstract: Prediction of data values to be read from memory by a microprocessor for load operations. In one aspect, a method for predicting a data value that will result from a load operation to be executed by the microprocessor includes accessing an entry in a load value prediction table that stores a predicted data value corresponding to the load operation. The predicted data value is provided as a result of the load operation without waiting for execution of the load operation to complete based on a confidence parameter stored in the entry compared to a dynamic confidence threshold.