Patents by Inventor John H. Cook

John H. Cook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7854424
    Abstract: A sectional fence assembly having a coupling device with a loop, disposed at an angle relative to the body of the fence section is disposed on one side of the fence section body and a hook is disposed on the opposing side of the fence section body. A plurality of such fence sections may be coupled in series.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: December 21, 2010
    Assignee: Ames True Temper, Inc.
    Inventors: John H. Cook, Stephen D. Hatcher
  • Patent number: 7726633
    Abstract: A molded plastic fence having a unitary front fence section and a unitary rear fence section is provided. The unitary front fence section and the unitary rear fence section are coupled together to form a fence without visible molding artifacts. To emulate a traditional wooden fence, the fence sections preferably include various fence elements such as posts, slats and rails. The fence elements on each fence section typically have a planar member with an inner side and a raised edge extending from the inner side. The molding artifacts are disposed on the inner sides of the fence elements. The unitary front fence section and a unitary rear fence section are coupled with the raised edges engaging each other. In this configuration the molding artifacts are hidden from view and the fence elements appear as solid.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: June 1, 2010
    Assignee: Ames True Temper, Inc.
    Inventors: John H. Cook, Stephen D. Hatcher
  • Publication number: 20090230371
    Abstract: A molded plastic fence having a unitary front fence section and a unitary rear fence section is provided. The unitary front fence section and the unitary rear fence section are coupled together to form a fence without visible molding artifacts. To emulate a traditional wooden fence, the fence sections preferably include various fence elements such as posts, slats and rails. The fence elements on each fence section typically have a planar member with an inner side and a raised edge extending from the inner side. The molding artifacts are disposed on the inner sides of the fence elements. The unitary front fence section and a unitary rear fence section are coupled with the raised edges engaging each other. In this configuration the molding artifacts are hidden from view and the fence elements appear as solid.
    Type: Application
    Filed: March 17, 2008
    Publication date: September 17, 2009
    Applicant: Ames True Temper, Inc.
    Inventors: John H. Cook, Stephen D. Hatcher
  • Patent number: 7076714
    Abstract: The problem of sequentially “squeezing” small fields of data in a larger data path in and out of a memory device can be solved in an algorithmically driven memory tester by defining sub-vectors to represent data in the small field, where a sequence of sub-vectors represents the data that would be represented by a full sized vector if such a full sized vector could be applied to the DUT. A programming construct in the programming language of the algorithmically driven memory tester allows sub-vectors to be defined, as well as an arbitrary mapping that each is to have. The arbitrary mapping is not static, but changes dynamically as different sub-vectors are encountered. Arbitrary dynamic mappings change as sub-vectors are processed, and may include the notion that, during the activity for a sub-vector, this (or these) bit(s) of a vector do not (presently) map to any pin at all of the DUT.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: July 11, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: John H Cook, III, Alan S Krech, Jr., Stephen D Jordan, Edmundo De La Puente, John M Freesman
  • Patent number: 6851076
    Abstract: The various functions that are desirable for interior test memory within a memory tester are implemented in Memory Sets each serving as the host for one or sometimes more of such functions. For certain classes of testing a portion of interior test memory can be used as a Stimulus Log RAM that operates as an ideal DUT to create the correct conditions that are to exist in an actual DUT after testing. The actual part can then be tested, while the expected receive vectors are taken from the Stimulus Log RAM, and the comparison results sent to an ECR, Tag RAM's, etc., as usual. In this way the test program does not have to create or contain within itself the particular receive vectors that are the expected response from the applied stimulus.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 1, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: John H Cook, III, Stephen D Jordan, Preet P Singh
  • Publication number: 20040078740
    Abstract: The problem of sequentially “squeezing” small fields of data in a larger data path in and out of a memory device can be solved in an algorithmically driven memory tester by defining sub-vectors to represent data in the small field, where a sequence of sub-vectors represents the data that would be represented by a full sized vector if such a full sized vector could be applied to the DUT. A programming construct in the programming language of the algorithmically driven memory tester allows sub-vectors to be defined, as well as an arbitrary mapping that each is to have. The arbitrary mapping is not static, but changes dynamically as different sub-vectors are encountered. Arbitrary dynamic mappings change as sub-vectors are processed, and may include the notion that, during the activity for a sub-vector, this (or these) bit(s) of a vector do not (presently) map to any pin at all of the DUT.
    Type: Application
    Filed: October 10, 2003
    Publication date: April 22, 2004
    Inventors: John H. Cook, Alan S. Krech, Stephen D. Jordan, Edmundo De La Puente, John M. Freesman
  • Patent number: 6320812
    Abstract: DRAM speed of operation in an Error Catch RAM can be increased by a combination of interleaving signals for different Banks of memory in a Group thereof and multiplexing between those Groups of Banks. A three-way multiplexing between three Groups of four Banks each, combined with a flexible four-fold interleaving scheme for signals to a Group produces an increase in speed approaching a factor of twelve, while requiring only three memory busses. Each of the twelve Banks represents the entire available address space, and any individual write cycle might access any one of the twelve Banks. A utility mechanism composes results for all twelve Banks during a read cycle at an address into a unified result. There is a mechanism to track of the integrity of the composed results, as further write operations can produce the need for another composing step. There are four Memory Sets, two are “internal” SRAM's and two are “external” DRAM's.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: November 20, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: John H. Cook, III, Preet P. Singh, Edmundo De la Puente
  • Patent number: 6199852
    Abstract: In a stapler for variably stapling a set or stack of sheets manually inserted through the stapler entrance path with different orientations, there is a sheet guide system with movable guide members automatically differently repositioned into different sheet guiding positions in the entrance path by the sheet stack insertion and its angle of insertion, including switching in between a corner angled stapling alignment position and a linear sheet edge aligned stapling position, respectively differently positioning the sheet stack for stapling. It may include a base plate, a pair of guide elements movably mounted on the base plate, and a fixed registration wall. The guide members in the corner angled stapling position may present opposing converging 45 degree angled edge registration surfaces to the inserted sheet stack. For edge stapling, the same guide members and/or the registration wall may present one, or two straight edge registration surfaces to the inserted stack.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: March 13, 2001
    Assignee: Xerox Corporation
    Inventors: David S. Visick, John H. Cook
  • Patent number: 6173949
    Abstract: In a stapler for variably stapling a set or stack of sheets manually inserted through the stapler entrance path with different orientations, there is a sheet guide system with movable guide members automatically differently repositioned into different sheet guiding positions in the entrance path by the sheet stack insertion and its angle of insertion, including switching in between a corner angled stapling alignment position and a linear sheet edge aligned stapling position, respectively differently positioning the sheet stack for stapling. It may include a base plate, a pair of guide elements movably mounted on the base plate, and a fixed registration wall. The guide members in the corner angled stapling position may present opposing converging 45 degree angled edge registration surfaces to the inserted sheet stack. For edge stapling, the same guide members and/or the registration wall may present one, or two straight edge registration surfaces to the inserted stack.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: January 16, 2001
    Assignee: Xerox Corporation
    Inventors: David S. Visick, John H. Cook
  • Patent number: 5512319
    Abstract: The present invention is directed to a method of applying a polyurethane foam to a fabric and the product produced thereof. This method involves (a) coating the fabric with a silicone surfactant dissolved in water, and (b) expanding the polyurethane foaming mixture in contact with the coated portion of the fabric.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: April 30, 1996
    Assignee: BASF Corporation
    Inventors: John H. Cook, Egils Grinbergs
  • Patent number: 4353955
    Abstract: The present invention is directed to a method of applying a polyurethane foam to a fabric and the product produced thereof. This method involves:(a) coating the fabric with a silicone surfactant, and(b) expanding the polyurethane foaming mixture in contact with the coated portion of the fabric.
    Type: Grant
    Filed: November 12, 1981
    Date of Patent: October 12, 1982
    Assignee: BASF Wyandotte Corporation
    Inventor: John H. Cook
  • Patent number: 3973699
    Abstract: A development system for use in electrostatographic automatic imaging machines is described. The system includes an apparatus comprising a cartridge having a tubular housing with a piston slideably mounted in the housing defining a set of chambers and means adapted for engagement with an external drive for advancing the piston along the housing. Outlet and inlet means communicating with chambers respectively have means for sealing the inlet and outlet means are also provided. This apparatus comprises a liquid developer system to develop latent images on a photoconductive surface in an expedient fashion which avoids spillage of the liquid developer.
    Type: Grant
    Filed: June 11, 1974
    Date of Patent: August 10, 1976
    Assignee: Xerox Corporation
    Inventor: John H. Cook
  • Patent number: D577831
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: September 30, 2008
    Assignee: Ames True Temper, Inc.
    Inventors: John H. Cook, Stephen D. Hatcher
  • Patent number: D579574
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: October 28, 2008
    Assignee: Ames True Temper, Inc.
    Inventors: John H. Cook, Stephen D. Hatcher