Patents by Inventor John H. Dungan

John H. Dungan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7583513
    Abstract: A device includes a plane metallization layer, and a plane plated through hole attached to the plane metallization layer and terminating at the at a major exterior surface with a plurality of component mounting pads. The plated through hole is attached to the plane metallization layer. The plane plated through hole is electrically isolated from the plurality of component mounting pads at the exterior surface. A method for testing the device includes contacting the signal carrying through hole, and contacting the plane through hole, and checking for current flow between the signal carrying through hole and the plane through hole. If current flows between the signal carrying through hole and the plane through hole the device fails. If no current flows between the signal carrying through hole and the plane through hole the device passes.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: David W Boggs, John H Dungan, Daryl A Sato
  • Patent number: 7385288
    Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: June 10, 2008
    Assignee: Intel Corporation
    Inventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
  • Patent number: 7325303
    Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
  • Patent number: 7241680
    Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: July 10, 2007
    Assignee: Intel Corporation
    Inventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
  • Patent number: 7201583
    Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
  • Patent number: 7084354
    Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: August 1, 2006
    Assignee: Intel Corporation
    Inventors: David W. Boggs, Daryl A. Sato, John H. Dungan, Gary I. Paek
  • Patent number: 6941537
    Abstract: A standoff device provides predetermined control of a standoff distance between electrical components mounted together with opposing conductive grid array patterns. In an embodiment, a predetermined electrical function is provided by the device to at least one of the electrical components. The standoff device comprises a plurality of rigid one-piece standoff pins which, in an embodiment, contains one or more stops which buttress against the electrical components to serve as a distancing control structure. In an embodiment, the standoff device is integral with one of the electrical components.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: September 6, 2005
    Assignee: Intel Corporation
    Inventors: Rebecca A. Jessep, David W. Boggs, Carolyn McCormick, John H. Dungan, Daryl A. Sato
  • Publication number: 20040231886
    Abstract: An apparatus and method for providing a vented blind via in pad of a printed circuit board (PCB). A vent in the blind via in pad to allow gases formed during reflow soldering to escape from the solder joint. In one embodiment, the vent extends from the outer edge of the pad to the blind via. In another embodiment, a method includes forming a blind via in pad having a vent.
    Type: Application
    Filed: June 17, 2004
    Publication date: November 25, 2004
    Inventors: David W. Boggs, John H. Dungan, Gary I. Paek, Daryl A. Sato
  • Publication number: 20040219342
    Abstract: An electronic substrate for interconnecting electronic components comprises a substrate having one or more conductive inner layers and one or more interconnect cavities extending into the substrate to expose one or more of the inner layers.
    Type: Application
    Filed: December 31, 2003
    Publication date: November 4, 2004
    Inventors: David W. Boggs, Daryl A. Sato, John H. Dungan, Gary Paek
  • Patent number: 6787443
    Abstract: An apparatus and method for providing a vented blind via in pad of a printed circuit board (PCB). A vent in the blind via in pad to allow gases formed during reflow soldering to escape from the solder joint. In one embodiment, the vent extends from the outer edge of the pad to the blind via. In another embodiment, a method includes forming a blind via in pad having a vent.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: September 7, 2004
    Assignee: Intel Corporation
    Inventors: David W. Boggs, John H. Dungan, Gary I. Paek, Daryl A. Sato
  • Patent number: 6667090
    Abstract: A registration coupon is provided for a printed circuit board or other substrate. The registration coupon may be used to determine a hole-to-outer layer feature registration and a solder mask registration. The registration coupon may include a registration hole provided on the circuit board, a metal pad and an anti-pad provided on the circuit board about the registration hole, and a solder mask covering the metal pad.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: David W. Boggs, Rebecca A. Jessep, Carolyn McCormick, Daryl A. Sato, John H. Dungan
  • Publication number: 20030231474
    Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 18, 2003
    Inventors: David W. Boggs, Daryl A. Sato, John H. Dungan, Gary I. Paek
  • Publication number: 20030145460
    Abstract: Standoff arrangements to control distance and provide electrical function.
    Type: Application
    Filed: February 7, 2002
    Publication date: August 7, 2003
    Inventors: Rebecca A. Jessep, David W. Boggs, Carolyn McCormick, John H. Dungan, Daryl A. Sato
  • Patent number: 6580174
    Abstract: An apparatus that includes a substrate, one or more via in pads in the substrate; and one or more vents in at least one of the one or more via in pads, the one or more vents connecting an outer diameter of at least one of the one or more via in pads to a diameter larger than the via.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: June 17, 2003
    Assignee: Intel Corporation
    Inventors: Carolyn R. McCormick, Rebecca A. Jessep, John H. Dungan, David W. Boggs, Daryl A. Sato
  • Publication number: 20030064546
    Abstract: An apparatus that includes a substrate, one or more via in pads in the substrate; and one or more vents in at least one of the one or more via in pads.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Carolyn R. McCormick, Rebecca A. Jessep, John H. Dungan, David W. Boggs, Daryl A. Sato
  • Publication number: 20030056365
    Abstract: A registration coupon is provided for a printed circuit board or other substrate. The registration coupon may be used to determine a hole-to-outer layer feature registration and a solder mask registration. The registration coupon may include a registration hole provided on the circuit board, a metal pad and an anti-pad provided on the circuit board about the registration hole, and a solder mask covering the metal pad.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 27, 2003
    Inventors: David W. Boggs, Rebecca A. Jessep, Carolyn McCormick, Daryl A. Sato, John H. Dungan