Abstract: A method of sputter deposition for improved side wall and bottom coverage of high aspect ratio features on a substrate includes alternatingly exposing the substrate having high aspect ratio features to a collimated sputtered particle flux and a less-collimated sputtered particle flux until a desired deposition thickness is reached. A confining magnetic field may be used to reduce electron losses at process chamber walls, allowing for improved collimation of the collimated flux. The substrate may also be heated or biased during exposure to the less-collimated flux to increase the good side wall and step coverage of the less-collimated flux, and cooled or reverse-biased during exposure to the collimated flux to increase the good bottom coverage of the collimated flux. Alternatively, the substrate may be exposed to only a collimated flux, but good sidewall coverage by be achieved by alternating the temperature and/or bias of the substrate to provide the desired side wall and step coverage.

Abstract: A semiconductor device having low-leakage borderless contacts is formed by etching contact openings adjacent first and second electronic elements of opposite dopant type, conformally depositing a thin doped polysilicon layer, protecting the electronic element of similar dopant-type, removing the thin doped polysilicon layer adjacent the oppositely doped electronic element, diffusing dopant from said polysilicon layer into a side wall of the electronic element of similar dopant-type, and then depositing tungsten within the contact openings.

Abstract: The invention provides a method for electrically connecting a trench capacitor and a diffusion region, and also for electrically connecting a trench capacitor or a diffusion region with external circuitry in a semiconductor device. The method provides for formation of a strap or bridge contact by formation of strap holes exposing the electrical elements utilizing an oxide insulation layer and a nitride etch stop and a highly selective oxide:nitride etch and a selective nitride:oxide etch. The strap holes may then be filled with an electrical conductor.

Abstract: A passivating layer is deposited over an integrated circuit device, conventionally fabricated using silicidation, after which an insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above the gate. The portion of the passivating layer above the gate is removed with little or no effect on the insulating layer or gate. A trench above one or both junctions (source or drain) is formed by removing insulation using the passivating layer as an etch stop, then removing a portion of the passivating layer above the junction with little or no effect on the junction or any isolation region present. The gate may be further silicided, and the opening above the gate and the trench above the junction may each be planarly filled with a low sheet resistance conductive material, forming contacts. The contact above the junction may be borderless.

Abstract: In a reactive ion plating process utilizing radio frequency power, the rate of evaporation of a noble metal such as ruthenium or iridium, the rate of evaporation of a valve metal such as titanium, and the partial oxygen pressure are adjusted to produce electrically conductive mixed metal oxide ceramic coating on a valve metal substrate. The noble metal constitutes 10-20 percent of the metal atoms in the coating. The coated substrate can sustain 150 amperes per square meter of exposed coating surface in fresh water electrolyte for at least 20 hours, and preferably at least 75 hours, without an excessive increase in the voltage level required to maintain that current density.