Abstract: A Lock register can be associated with a mailbox. The Lock register can store a claim ID of a process that has allocated the mailbox. The Lock register can include a Lock port and a Lock Clear port, used to claim and release the Lock register. The Lock register only permits data to be written to the Lock Register when the Lock register is not currently allocated, and the Lock Clear port only permits the process that has allocated the Lock register to write a value.

Abstract: Embodiments of the inventive concept include a system and method for computing a partial parity error correcting code. Check bits are computed from subsets of the data bits and stored. When the data bits are read, the check bits can be recomputed from the read data bits and compared with the stored check bits to generate a syndrome value. The syndrome value can identify which data bits and/or check bits are in error and correct for the errors.

Abstract: Embodiments of the inventive concept include a system and method for correcting multi-bit errors. A data vector and corresponding check vector can be stored. Error correcting circuitry can be used to identify which bits in the data vector, if any, are in error. Using information from a fault information storage, a correction vector can also be applied to the data vector to generate an alternate data vector. Error correcting circuitry can be used to identify which bits in the alternate data vector, if any, are in error. A final data vector can then be generated based on the data vector, the alternate data vector, and the results of the error correcting circuitries, which can then be returned as the read data vector.

Abstract: A Lock register can be associated with a mailbox. The Lock register can store a claim ID of a process that has allocated the mailbox. The Lock register can include a Lock port and a Lock Clear port, used to claim and release the Lock register. The Lock register only permits data to be written to the Lock Register when the Lock register is not currently allocated, and the Lock Clear port only permits the process that has allocated the Lock register to write a value.

Abstract: According to one general aspect, an apparatus may include a data word storage, and an error correction code generator. The data word storage may be configured to store a word of data, parity bits, and a partial word flag. The partial write flag may be configured to indicate whether a previous write operation was a full write or a partial write to the word of data. The ECC generator may be configured to dynamically generate an ECC during a write operation. If the write operation includes a full write to the word of data, the ECC generator may be configured to generate a first ECC based, at least in part, upon the word of data, the plurality of parity bits, and the partial word flag. If the write operation includes a partial write to the word of data, the ECC generator may be configured to generate a second ECC.

Abstract: The present invention defines a system and method of routing packets using a hardware-based route cache with prefix length. When a router receives a packet, the router first searches for the routing information in the hardware-based route cache and if a match is found, the packet is forwarded to according to the routing information. The hardware-based route cache can be configured according to a search scheme employed by the router. The hardware-based route cache can be configured to provide network address length information for the destination addresses included in an incoming packet.

Abstract: The present invention describes a system and method of improving packet forwarding throughput in a router by reducing head of line blocking. In one embodiment of the present invention, incoming packets are stored in a packet reorder buffer. The packets are reordered for forwarding while maintaining the order of packets in a distinct flow. Packets belonging to a distinct flow require to be forwarded in the order that the router receives them. Packets from different flows are reordered such that their forwarding order can be different than the order in which they were received. Packets from the same flow are sent out in the same order as the router receives them.

Abstract: A data channel for a digital tester includes a random access local memory containing a main vector sequence, a subroutine vector sequence, and a test vector list. An index register is loaded with the address of the first vector in the list of vectors that is to be inserted as a variable into a vector stream. A sequence instruction selects the index register as the source of a test vector address when a variable vector is to be inserted into the vector stream at a point in a subroutine. The sequence instruction also resets the index register to a state which determines the address of the next variable to be inserted into the test vector pattern.

Abstract: A method and system for loading test data into individual pin memories of an automatic digital test system, particularly of the in-circuit type. Test data in the form of test vectors are accessed from a test vector store simultaneously with the access of a digital test pin selection signal. The test pin selection signal accessed with the test data is then used to selectively load the test data into a pin memory identified by the pin selection signal, thereby permitting the loading of test data into any one of a group of individual pin memories. In the preferrred embodiment the test data, a test vector, is stored in a test vector store in association with a test pin selection signal. When the test vector is read from memory, the test pin selection signal is also read by the same address signal.