Patents by Inventor John H. Magerlein
John H. Magerlein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8581392Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling.Type: GrantFiled: December 7, 2012Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: John Ulrich Knickerbocker, John H. Magerlein
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Patent number: 8421220Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.Type: GrantFiled: February 3, 2012Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: John Ulrich Knickerbocker, John H. Magerlein
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Publication number: 20120133051Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.Type: ApplicationFiled: February 3, 2012Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Ulrich Knickerbocker, John H. Magerlein
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Patent number: 8110415Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.Type: GrantFiled: April 3, 2008Date of Patent: February 7, 2012Assignee: International Business Machines CorporationInventors: John Ulrich Knickerbocker, John H. Magerlein
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Patent number: 8097492Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.Type: GrantFiled: December 24, 2008Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: John H. Magerlein, Chirag S. Patel, Edmund J. Sprogis, Herbert I. Stoller
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Publication number: 20110205708Abstract: A plurality of heat-dissipating electronic chips are arranged in a vertical chip stack. The electronic chips have electronic components thereon. A cold plate is secured to a back side of the chip stack. A silicon carrier sandwich, defining a fluid cavity, is secured to a front side of the chip stack. An inlet manifold is configured to supply cooling fluid to the cold plate and the fluid cavity of the silicon carrier sandwich. An outlet manifold is configured to receive the cooling fluid from the cold plate and the fluid cavity of the silicon carrier sandwich. The cold plate, the silicon carrier sandwich, the inlet manifold, and the outlet manifold are configured and dimensioned to electrically isolate the cooling fluid from the electronic components. A method of operating an electronic apparatus and a method of manufacturing an electronic apparatus are also disclosed.Type: ApplicationFiled: February 24, 2010Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. Andry, Thomas J. Brunschwiler, Evan G. Colgan, John H. Magerlein
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Patent number: 7990711Abstract: A plurality of heat-dissipating electronic chips are arranged in a vertical chip stack. The electronic chips have electronic components thereon. A cold plate is secured to a back side of the chip stack. A silicon carrier sandwich, defining a fluid cavity, is secured to a front side of the chip stack. An inlet manifold is configured to supply cooling fluid to the cold plate and the fluid cavity of the silicon carrier sandwich. An outlet manifold is configured to receive the cooling fluid from the cold plate and the fluid cavity of the silicon carrier sandwich. The cold plate, the silicon carrier sandwich, the inlet manifold, and the outlet manifold are configured and dimensioned to electrically isolate the cooling fluid from the electronic components. A method of operating an electronic apparatus and a method of manufacturing an electronic apparatus are also disclosed.Type: GrantFiled: February 24, 2010Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Paul S. Andry, Thomas J. Brunschwiler, Evan G. Colgan, John H. Magerlein
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Patent number: 7928562Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.Type: GrantFiled: July 22, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Amilcar R. Arvelo, Evan G. Colgan, John H. Magerlein, Kenneth C. Marston, Kathryn C. Rivera, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei, Jeffrey A. Zitz
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Patent number: 7855442Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.Type: GrantFiled: January 8, 2007Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: John H. Magerlein, Chirag S. Patel, Edmund J. Sprogis, Herbert I. Stoller
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Patent number: 7829427Abstract: A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.Type: GrantFiled: November 5, 2009Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
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Publication number: 20100047990Abstract: A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.Type: ApplicationFiled: November 5, 2009Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
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Publication number: 20100019377Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.Type: ApplicationFiled: July 22, 2008Publication date: January 28, 2010Applicant: International Business Machines CorporationInventors: Amilcar R. Arvelo, Evan G. Colgan, John H. Magerlein, Kenneth C. Marston, Kathryn C. Rivera, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei, Jeffrey A. Zitz
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Patent number: 7638406Abstract: A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.Type: GrantFiled: December 28, 2005Date of Patent: December 29, 2009Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
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Publication number: 20090251862Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.Type: ApplicationFiled: April 3, 2008Publication date: October 8, 2009Applicant: International Business Machines CorporationInventors: John Ulrich Knickerbocker, John H. Magerlein
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Patent number: 7581314Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.Type: GrantFiled: February 21, 2006Date of Patent: September 1, 2009Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John M. Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John H. Magerlein, Kenneth Stein, Richard P. Volant, James A. Tornello, Jennifer Lund
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Publication number: 20090174059Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.Type: ApplicationFiled: December 24, 2008Publication date: July 9, 2009Inventors: John H. Magerlein, Chirag S. Patel, Edmund J. Sprogis, Herbert I. Stroller
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Patent number: 7202764Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.Type: GrantFiled: July 8, 2003Date of Patent: April 10, 2007Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John M. Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John H. Magerlein, Kenneth Stein, Richard P. Volant, James A. Tornello, Jennifer Lund
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Patent number: 7189595Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.Type: GrantFiled: June 16, 2004Date of Patent: March 13, 2007Assignee: International Business Machines CorporationInventors: John H. Magerlein, Chirag S. Patel, Edmund J. Sprogis, Herbert I. Stoller
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Patent number: 7128472Abstract: An optoelectronic assembly for a computer system includes an electronic chip(s), a substrate, an electrical signaling medium, an optoelectronic transducer, and an optical coupling guide. The electronic chip(s) is in communication with the substrate, which is in communication with a first end of the electrical signaling medium. A second end of the electrical signaling medium is in communication with the optoelectronic transducer, and includes the optical coupling guide for aligning an optical signaling medium with the optoelectronic transducer. An electrical signal from the electronic chip is communicated to the optoelectronic transducer via the substrate and the electrical signaling medium. The optical transducer and electronic chip(s) share a common heat spreader, and communication to other groups of electronic chip(s) is done without the need for communication via a second level electrical package.Type: GrantFiled: July 31, 2003Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: Alan F. Benner, Evan G. Colgan, How Tzu Lin, John H. Magerlein, Frank L. Pompeo, Subhash L. Shinde, Daniel J. Stigliani, Jr.
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Patent number: 7068138Abstract: An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.Type: GrantFiled: January 29, 2004Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant