Abstract: A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated.

Abstract: A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated.

Abstract: Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are disclosed. The various voltage levels can be produced by charge pump and regulator circuitry within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect of the invention, charge pump and regulator circuitry is not only provided within each of the memory blocks of a memory system, but also the charge pump and regulator circuits are not used to supply voltage signals to their own memory blocks. Instead, the charge pump and regulator circuits are used to supply voltage signals to other memory blocks.

Abstract: A technique for controlling the soft-program current in virtual-ground FLASH memory arrays is described. It is based on biasing the array bit-lines such that all current supplied to the array is used entirely towards the soft-programming of selected cells. The result is control of the soft-programming current and the programming rate of individual cell pairs. The benefit of soft-programming is then realized during the actual cell programming with the improved control of current and program rate. This is described with respect to an embodiment that uses source-side injection as the means for programming memory cells and with respect to a second embodiment based on a cell with dual floating gates.

Abstract: A technique for controlling the soft-program current in virtual-ground FLASH memory arrays is described. It is based on biasing the array bit-lines such that all current supplied to the array is used entirely towards the soft-programming of selected cells. The result is control of the soft-programming current and the programming rate of individual cell pairs. The benefit of soft-programming is then realized during the actual cell programming with the improved control of current and program rate. This is described with respect to an embodiment that uses source-side injection as the means for programming memory cells and with respect to a second embodiment based on a cell with dual floating gates.

Abstract: Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are disclosed. The various voltage levels can be produced by charge pump and regulator circuitry within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect of the invention, charge pump and regulator circuitry is not only provided within each of the memory blocks of a memory system, but also the charge pump and regulator circuits are not used to supply voltage signals to their own memory blocks. Instead, the charge pump and regulator circuits are used to supply voltage signals to other memory blocks.

Abstract: An internal supply generator includes a charge pump, at least one regulator and a pump controller. The charge pump generates a charge pump signal whose voltage is higher than an input supply voltage. Each regulator produces a generally stable internal supply from the charge pump signal. The pump controller activates the charge pump whenever the charge pump signal falls to within a predetermined voltage of the voltage level of one of the internal supplies.

Abstract: A charge pump whose charge transfer switches are formed of charge transfer transistors and single pole, double throw (SPDT) switches each of which controls the gate of its corresponding transistor. Each SPDT switch has two throw contacts, one which is connected to the left diffusion of its corresponding charge transfer transistor and the other of which is connected to ground. Thus, the SPDT switch selectively connects the gate of the charge transfer transistor it controls between a diode connection (the first contact) and ground (the second contact). As a result, the charge transfer switches of the present invention are both fully on (when diode-connected) or fully off (when connected to ground).

Abstract: A unit for maintaining the value of information regarding the state of a device during battery power includes one local latch per bit of state to be maintained. The latch is powered by a switched power supply which switches between main and battery power supplies. The latch latches the value of the bit of state when the value of the bit of state is valid and the power of the device is significant and maintains the value otherwise, typically during battery operation.

Abstract: A unit for stabilizing the voltage on a capacitive node of a memory array, such as a common node bit line (CNBL), is disclosed. The unit includes an amplifier connected to the CNBL line and to one voltage source and a leaker connected to the CNBL line and to the other voltage supply, where the two voltage supplies can be the positive and ground supplies. The leaker is much smaller then the amplifier thereby to remove current from the CNBL line when there is little or no activity in The memory array. An alternative version of the unit which is also operative for standby operation is disclosed. In this embodiment, there is a switchable high power unit activatable during an active mode and a low power unit. Both units include an amplifier and a leaker connected as in the previous embodiment. The leakers are much smaller then the amplifiers and the amplifier of the high power unit is much larger than the amplifier of the low power unit.

Abstract: An embodiment of this invention provides an integrated circuit (IC) having a configurable peripheral port which includes an input/output pin, a multiplexer coupled to the input/output pin, volatile configuration bits to control the multiplexer, and non-volatile configuration bits to control the multiplexer and override the volatile configuration bits. One embodiment of an IC also includes a peripheral port as above and functional units, such as programmable array logic (PAL) and erasable programmable read only memory (EPROM), coupled to the multiplexer. In another embodiment, a non-volatile configuration bit from a functional unit configures an input/output pin when the configuration bit is not needed by the functional unit.