Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

Abstract: A semiconductor device is formed to include a fin structure, a first trench at a first lateral end of the fin, a second trench at a second lateral end of the fin, and a filler filled on a first traverse side of the fin and a second traverse side of the fin. The filler is contained between the first trench and the second trench, and oxidized in-place to cause a stress to be exerted on the first and second traverse sides of the fin, the stress causing the fin to exhibit a tensile strain in a lateral running direction of the fin.

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

Abstract: Processes and overturned thin film device structures generally include a gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the gate and the source/drain contacts include a self-aligned step height.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A semiconductor structure includes a plurality of field effect transistors formed on a substrate including p-type doped field effect transistors (pFETs) and n-type doped field effect transistors (nFETs). A self-aligned buried local interconnect electrically connects a bottom source or drain region of the pFET with an adjacent bottom source or drain region of the nFET. The self-aligned buried local interconnect is serially aligned with and intermediate opposing ends of a gate electrode. Other embodiments include methods for forming the buried local interconnect.

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

Abstract: A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

Abstract: A vertical transistor device includes a vertically oriented channel semiconductor structure, a bottom source/drain (S/D) region, a top source/drain (S/D) region, and a gate structure positioned around the vertically oriented channel semiconductor structure, above the bottom source/drain (S/D) region, and below the top source/drain (S/D) region. The gate structure includes a gate electrode and a gate insulation layer positioned between the gate electrode and at least a portion of the vertically oriented channel semiconductor structure. A top spacer is positioned between the gate electrode and at least a portion of the top source/drain (S/D) region, a bottom spacer is positioned between the gate electrode and at least a portion of the bottom source/drain (S/D) region, and a gate cap is positioned around an outer perimeter surface of the gate structure, wherein the top spacer, the bottom spacer, and the gate cap all include a same insulating material.

Abstract: A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Abstract: A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.

Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

Abstract: A first TS is coupled to first S/D over first fin, second TS coupled to second S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth S/D over second fin, gate metal over first and second fins, and gate cap over gate metal. First TS cap is on first TS, second TS cap on second TS, third TS cap on third TS, and fourth TS cap on fourth TS. ILD is formed on top of gate cap and first through fourth TS caps. First opening is through ILD and second TS cap such that part of gate metal is exposed, after removing part of gate cap. Second opening is through ILD to expose another part of gate metal. Combined gate metal contact and local metal connection is formed in first opening and individual gate metal contact is formed in second opening.