Abstract: A system and method for radar detection and calibration. By measuring the true range of a calibration target on entry to the radar's detection zone, the actual detection capability of the radar in current atmospheric conditions with the actual radar can be determined. The radar system is also adapted to determine a sensed position at a sensed time of a target in the radar's detection zone. A calibration target, preferably an unmanned air vehicle (UAV), includes a position device for determining the actual position of the calibration target. A calibration device communicates with the radar system and the calibration target and receives the sensed and actual positions of the calibration target. The calibration device calculates the error between the sensed position and the actual position and adjusts the radar system to minimize the error. The target may include a signal augmentation device to augment the radar cross-section of the target to replicate the radar cross-sections of targets of various types.

Abstract: A system and method for radar detection and calibration. By measuring the true range of a calibration target on entry to the radar's detection zone, the actual detection capability of the radar in current atmospheric conditions with the actual radar can be determined. The radar system is also adapted to determine a sensed position at a sensed time of a target in the radar's detection zone. A calibration target, preferably an unmanned air vehicle (UAV), includes a position device for determining the actual position of the calibration target. A calibration device communicates with the radar system and the calibration target and receives the sensed and actual positions of the calibration target. The calibration device calculates the error between the sensed position and the actual position and adjusts the radar system to minimize the error. The target may include a signal augmentation device to augment the radar cross-section of the target to replicate the radar cross-sections of targets of various types.

Abstract: A digital processor system that includes a processor interface to an external memory. The interface to the external memory includes an information transfer bus to transfer information between the processor and the external memory and control circuitry to regulate the information on the information bus. This control circuitry includes the capability to delay the reading of information on the memory in order to allow for memory accesses to a slow memory. This delay capability is a selectable feature that is selected upon initialization of the processor.