Abstract: The invention is a method of administering therapeutic iodine for treating a disorder in a mammal. The invention comprises a step of feeding said mammal an effective amount of an oxidant for an iodine species and an iodine reductant which will cause oxidation-reduction reactions upon contact with the gastric juices present in the stomach of the mammal. This is done such that molecular iodine is generated in vivo at a ratio of molecular iodine to total iodine of above at least about 0.65. The invention also discloses a non-aqueous pharmaceutically acceptable carrier with said oxidant and reductant having the ability to cause oxidation-reduction reactions upon contact with the gastric juices present in the stomach of said mammal and in an amount sufficient to generate molecular iodine, in vivo, at a ratio of molecular iodine to total iodine of above at least about 0.65.

Abstract: A hat display structure is shown to include an opaque substrate, a transparent layer connected to the substrate by snaps or the like at its edges, and a multi-piece frame, which, in turn, is snapped onto the layer. The transparent layer is formed to, in part, conform to the shape of an athletic hat or cap, with a bill, which has its crown folded in half, with the back half folded inwardly of the front half. Provision is also made in the layer for housing a plaque or the like in order designate or explain the significance of the hat or cap displayed.

Abstract: A microbial decontamination system includes a chamber for housing items to be decontaminated as well as a source of one or more iodine-containing fluids that are conveyed to the chamber as necessary. The system also includes a detector element for monitoring the concentration of free iodine within the chamber. A signal representative of the free iodine concentration is conveyed to a controller element which communicates with receptacles for housing the iodine-containing fluids so that additional iodine-containing fluids may be added to maintain the free iodine concentration within the chamber at a desired level.

Abstract: An implementation efficient interrupt select mechanism which allocates interrupt flags between N interrupt requestors, e.g. communication channels. A multi-channel controller provides the select mechanism with control signals and asserts an interrupt request when a channel, being visited by a scanner, which may be incorporated into the controller, is asserting an interrupt request. If the interrupt flag is available, the number of the channel asserting the request is locked into a latch. The latch remains locked until the interrupt request is cleared, a control signal is received from the controller and the channel being visited by the scanner equals the channel number stored in the latch. The scanner increments from channel to channel regardless of the assertion of the interrupt flag or the locking of the latch. In this manner, a single scanner may be used with any number or interrupt select mechanisms.

Abstract: Two devices HR and FR are coupled to a bus with a common memory via a port controller. Device HR requires a high (or maximum) average rate of access, device FR requires a fast response (minimum latency) in establishing access. Request signals HRQ, FRQ from the devices are latched by latches 20 and 21, passed as HRX, FRX through an arbitration or resolver circuit 22 as HRY, FRY to a sequence control unit 23 to initiate an access cycle. Cycle timing is determined by a delay line timebase circuit 24, which responds to a single change of level of a signal DLY (in either direction). Latch 21, when set, generates an request pending signal FRRP which is fed to the HR device to cause it to increase its cycle length so that the FR access cycle will finish before the next HR access cycle is initiated.

Abstract: Loop-back detection and signalling is achieved on any DS-0 channel that conforms to 56 kbps operation such as DDS in a DS-1 digital data transmission system. A standard DS-1 chip set (line interface unit, framer, and link layer controller) is used, coupled to 24 transmit and receive buffer means in the customer main memory. The framer detects control bits by using Channel Associate Signalling, (designed for digitising voice in-band signalling and not normally used for data transmission), in the incoming signal and interrupts the customer CPU, which determines from the framer which channel caused the interrupt, changes the mode of the relevant channel, checks that channel's receive buffer means for loop-back codes, and, if enough successive loop-back codes are found, copies the receive buffer means into the transmit buffer means (with code mapping) for as long as the loop-back condition exists.

Abstract: A system for affecting the flow of a fluid medium relative to an object including a plurality of surface deviations disposed on the surface of the object. The deviations are grouped into at least one set and the sets are arranged into at least one predetermined pattern. The deviations cover only a portion of the object's surface.