Abstract: Aspects of the present disclosure include systems, structures, integrated circuit (IC) packages or modules, circuits, and methods providing a transformer with first and second coils and a sense coil configured adjacent to and closely coupled with the second coil. The circuits, ICs and IC packages and modules may include various types of circuits. In some examples, IC packages or modules may include a galvanically-isolated gate driver or other high voltage circuit.

Abstract: Methods and apparatus for a desaturation circuit having a temperature compensated voltage threshold for protecting a power transistor, such as a FET. A comparator module has a first input compared to a voltage source associated with current through the FET and a second input coupled to the voltage threshold circuit. As a resistance of the FET changes due to temperature changes, the voltage threshold changes to compensate for the resistance change of the FET.

Abstract: Methods and apparatus for capacitively isolated first communication channels with common mode noise suppression. In embodiments, a driver on the first circuit transmits a data signal on the first communication channel to a receiver on the second circuit. A common mode suppression circuit on the second circuit is coupled to the receiver, output of the suppression circuit is coupled to a node between the first capacitor and the resistor network and an input is coupled to a ground of the first circuit via a second capacitor. The common mode suppression circuit is configured to detect a common mode movement signal due to a noise pulse to the second circuit on the input and generate a corresponding signal on the output to maintain a current level across the resistor network for suppressing common mode noise from the pulse.

Abstract: Methods and apparatus for a desaturation circuit having a temperature compensated voltage threshold for protecting a power transistor, such as a FET. A comparator module has a first input to a voltage source associated with current through the FET and a second input coupled to the voltage threshold circuit. As a resistance of the FET changes due to temperature changes, the voltage threshold changes to compensate for the resistance change of the FET.

Abstract: Aspects of the present disclosure include systems, structures, integrated circuit (IC) packages or modules, circuits, and methods providing a transformer with first and second coils and a sense coil configured adjacent to and closely coupled with the second coil to reduce the effects of common mode transients. The circuits, ICs and IC packages and modules may include various types of circuits. In some examples, IC packages or modules may include a galvanically-isolated gate driver or other high voltage circuit.

Abstract: Methods and apparatus for a differential receiver having a differential latch. The latch can include first and second circuits each having first and second inputs to receive a differential input signal and first and second outputs to output a differential output signal. An offset structure includes a bandgap reference circuit with a first current source and a resistor, wherein the offset compensation structure provides a stable threshold for an input signal on the first and second inputs.

Abstract: Methods and apparatus for a differential receiver having a differential latch. The latch can include first and second circuits each having first and second inputs to receive a differential input signal and first and second outputs to output a differential output signal. An offset structure includes a bandgap reference circuit with a first current source and a resistor, wherein the offset compensation structure provides a stable threshold for an input signal on the first and second inputs.

Abstract: Methods and apparatus for capacitively isolated first communication channels with common mode noise suppression. In embodiments, a driver on the first circuit transmits a data signal on the first communication channel to a receiver on the second circuit. A common mode suppression circuit on the second circuit is coupled to the receiver, output of the suppression circuit is coupled to a node between the first capacitor and the resistor network and an input is coupled to a ground of the first circuit via a second capacitor. The common mode suppression circuit is configured to detect a common mode movement signal due to a noise pulse to the second circuit on the input and generate a corresponding signal on the output to maintain a current level across the resistor network for suppressing common mode noise from the pulse.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. A corresponding method of deskewing a differential signal and a system and circuit therefor are also provided.

Abstract: Charge from a charge pump of a PLL is dumped to a loop filter of the PLL. The dumped charge is temporarily stored in a capacitor, between the charge pump and the loop filter. A voltage of the capacitor is shifted, while temporarily storing the dumped charge. Other embodiments are also described and claimed.

Abstract: A filter couples an output of a phase detector to an input of a voltage controlled oscillator. The filter has a first capacitor and a switch capacitor resistor that is in series with the first capacitor, between the first capacitor and the output of the phase detector. The switch capacitor resistor is to display a resistance that is obtained by switching back and forth a second capacitor to the first capacitor and to the phase detector output. Other embodiments are also described and claimed.

Abstract: A method that automatically generates a design for an analog phase lock loop (PLL) core in response to a desired clock frequency.

Abstract: A method that automatically generates a design for an analog phase lock loop (PLL) core in response to a desired clock frequency.

Abstract: A method and a digital circuit for synthesizing an input signal to produce an output signal are provided. The circuit includes a delay unit with a delay input and a delay output, a switch, and a controller. The selectively switch routes the input signal to the delay input whereafter the switch routes the delay output to the delay input. The controller controls the delay unit in response to the input signal and the output signal. A counter is provided to count a predetermined number of times the delay output is routed to the delay input whereafter the input signal is routed to the delay input to trigger the delay input. The digital circuit synthesizes the input signal to define a Delay-Locked loop (DLL) in which the delay unit is a voltage controlled delay line (VCDL). The invention extends to a computer program product executing the method and to an embedded circuit including the digital circuit.

Abstract: A method and a digital circuit for synthesizing an input signal to produce an output signal are provided. The circuit includes a delay unit with a delay input and a delay output, a switch, and a controller. The selectively switch routes the input signal to the delay input whereafter the switch routes the delay output to the delay input. The controller controls the delay unit in response to the input signal and the output signal. A counter is provided to count a predetermined number of times the delay output is routed to the delay input whereafter the input signal is routed to the delay input to trigger the delay input. The digital circuit synthesizes the input signal to define a Delay-Locked loop (DLL) in which the delay unit is a voltage controlled delay line (VCDL). The invention extends to a computer program product executing the method and to an embedded circuit including the digital circuit.

Abstract: A deposit system for storing delivered goods awaiting collection by the recipient comprising a storage container with access means having a wheel mounted for rotation to facilitate transport, securing means and locking means for attaching or detaching the storage container from the securing means.

Abstract: A bubble suppression apparatus is disclosed comprising: a first set of AND gates, wherein each AND gate within the first set has an input configured to receive a binary thermometer code value and one or more adjacent binary thermometer code values; and a second set of AND gates, wherein each AND gate within the second set has an input coupled to two or more outputs of the first set of AND gates.

Abstract: An apparatus having a white noise source which is coupled to a gain stage having an amplifier. The gain stage is coupled to a noise shaping stage which is also coupled to a decision circuit. Another apparatus having a white noise source which is differentially coupled to a gain stage that has a cascade of open loop amplifiers. The gain stage is differentially coupled to a noise shaping stage which is also differentially coupled to a decision circuit. A method that involves differentially coupling white noise into a gain stage. The white noise is differentially amplified with an amplifier which produces a first white noise signal. 1/f noise and offset voltage is substantially removed from said first white noise signal to produce a second white noise signal. A random sequence signal is produced by deciding whether the second white noise signal is a 1 or 0.