Abstract: A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.

Abstract: A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.

Abstract: A memory comprises: a substrate; a dielectric region formed on the substrate; a source-contacted layer formed in the dielectric region; a first source diffusion formed in the substrate; a first drain diffusion formed in the substrate; a first floating gate formed in the dielectric region; a first control gate formed in the dielectric region; a first erase gate formed in the dielectric region; and a first source diffusion via electrically coupling the first source diffusion to the source-contacted layer.

Abstract: A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles.

Abstract: A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles.

Abstract: An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided.

Abstract: A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles.

Abstract: An electrically erasable programmable read-only memory (EEPROM) with a ripple programming mode. Memory cells in an the EEPROM array include floating-gate transistors with control gates coupled to corresponding word lines, and drain electrodes coupled to corresponding bit lines. A memory cell is programmed by applying a high programming voltage to its control gate along with applying a high programming voltage to its drain. Multiple memory cells within a row can be programmed by applying the programming voltage to the word line of that row, during which multiple bit lines receive their programming voltage, without removing the word line programming voltage when changing the programming from one bit line to another.

Abstract: An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided.

Abstract: An electrically erasable programmable read-only memory (EEPROM) with a ripple programming mode. Memory cells in an the EEPROM array include floating-gate transistors with control gates coupled to corresponding word lines, and drain electrodes coupled to corresponding bit lines. A memory cell is programmed by applying a high programming voltage to its control gate along with applying a high programming voltage to its drain. Multiple memory cells within a row can be programmed by applying the programming voltage to the word line of that row, during which multiple bit lines receive their programming voltage, without removing the word line programming voltage when changing the programming from one bit line to another.

Abstract: An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side.

Abstract: An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side.