Patents by Inventor John Howson
John Howson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954759Abstract: A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. Indicators are determined for the graphics data items, whereby the indicator for a graphics data item indicates the number of tiles with which that graphics data item is associated. The graphics data items are evicted from the cache in accordance with the indicators of the graphics data items. For example, the indicator for a graphics data item may be a count of the number of tiles with which that graphics data item is associated, whereby the graphics data item(s) with the lowest count(s) is (are) evicted from the cache.Type: GrantFiled: December 7, 2022Date of Patent: April 9, 2024Assignee: Imagination Technologies LimitedInventors: Steven Fishwick, John Howson
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Patent number: 11928776Abstract: A graphics processing system performs hidden surface removal and texturing/shading on fragments of primitives. The system includes a primary depth buffer (PDB) for storing depth values of resolved fragments, and a secondary depth buffer (SDB) for storing depth values of unresolved fragments. Incoming fragments are depth tested against depth values from either the PDB or the SDB. When a fragment passes a depth test, its depth value is stored in the PDB if it is a resolved fragment (e.g. if it is opaque or translucent), and its depth value is stored in the SDB if it is an unresolved fragment (e.g. if it is a punch through fragment). This provides more opportunities for subsequent opaque objects to overwrite punch through fragments which passed a depth test, thereby reducing unnecessary processing and time which may be spent on fragments which ultimately will not contribute to the final rendered image.Type: GrantFiled: October 17, 2021Date of Patent: March 12, 2024Assignee: Imagination Technologies LimitedInventor: John Howson
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Patent number: 11887240Abstract: A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.Type: GrantFiled: January 19, 2022Date of Patent: January 30, 2024Assignee: Imagination Technologies LimitedInventors: John Howson, Steven Fishwick
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Publication number: 20230394615Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.Type: ApplicationFiled: August 21, 2023Publication date: December 7, 2023Inventors: John Howson, Jonathan Redshaw, Yoong Chert Foo
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Publication number: 20230396128Abstract: A power tool comprising a housing and a brushless direct-current (BLDC) motor disposed within the housing. The motor includes a stator and a rotor rotatable relative to the stator. The power tool is configured to generate a power output from the motor that is greater than 1200 continuous hot Watts out such that a quotient obtained by the power output measured in Watts (Wout), divided by an input measured in Volt-Amperes (Vain), and further divided by a volume of the power tool measured in cubic centimeters (cc), is greater than 600 Wout/Vain/cc.Type: ApplicationFiled: August 18, 2023Publication date: December 7, 2023Applicant: Black & Decker Inc.Inventors: John C. Vanko, Michael K. Forster, Matthew J. Velderman, John Howson
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Publication number: 20230334769Abstract: A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitives, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will subsequently be hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.Type: ApplicationFiled: June 19, 2023Publication date: October 19, 2023Inventors: Richard Broadhurst, John Howson, Robert Theed
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Patent number: 11770048Abstract: A power tool comprising a housing and a brushless direct-current (BLDC) motor disposed within the housing. The motor includes a stator and a rotor rotatable relative to the stator. The power tool is configured to generate a power output from the motor such that a quotient obtained by the power output measured in Watts (Wout), divided by an input measured in Volt-Amperes (Vain), and further divided by a diameter of the motor measured in meters (m), is greater than 10 Wout/Vain/m.Type: GrantFiled: November 8, 2021Date of Patent: September 26, 2023Assignee: BLACK & DECKER, INC.Inventors: John C. Vanko, Michael K. Forster, Matthew J. Velderman, John Howson
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Patent number: 11734788Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.Type: GrantFiled: October 29, 2021Date of Patent: August 22, 2023Assignee: Imagination Technologies LimitedInventors: John Howson, Jonathan Redshaw, Yoong Chert Foo
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Publication number: 20230260074Abstract: A graphics processing system for generating a rendering output includes geometry processing logic having first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block used in generating the rendering output.Type: ApplicationFiled: April 27, 2023Publication date: August 17, 2023Inventors: Robert Brigg, John Howson, Xile Yang
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Patent number: 11682163Abstract: A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitives, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will subsequently be hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.Type: GrantFiled: June 30, 2021Date of Patent: June 20, 2023Assignee: Imagination Technologies LimitedInventors: Richard Broadhurst, John Howson, Robert Theed
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Patent number: 11640648Abstract: A graphics processing system for generating a rendering output includes geometry processing logic and rasterization logic. The geometry processing logic includes first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to: divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one of the one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block that are to be used in generating the rendering output.Type: GrantFiled: October 11, 2021Date of Patent: May 2, 2023Assignee: Imagination Technologies LimitedInventors: Robert Brigg, John Howson, Xile Yang
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Publication number: 20230102320Abstract: A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. Indicators are determined for the graphics data items, whereby the indicator for a graphics data item indicates the number of tiles with which that graphics data item is associated. The graphics data items are evicted from the cache in accordance with the indicators of the graphics data items. For example, the indicator for a graphics data item may be a count of the number of tiles with which that graphics data item is associated, whereby the graphics data item(s) with the lowest count(s) is (are) evicted from the cache.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Inventors: Steven Fishwick, John Howson
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Patent number: 11551326Abstract: A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. Indicators are determined for the graphics data items, whereby the indicator for a graphics data item indicates the number of tiles with which that graphics data item is associated. The graphics data items are evicted from the cache in accordance with the indicators of the graphics data items. For example, the indicator for a graphics data item may be a count of the number of tiles with which that graphics data item is associated, whereby the graphics data item(s) with the lowest count(s) is (are) evicted from the cache.Type: GrantFiled: February 13, 2018Date of Patent: January 10, 2023Assignee: Imagination Technologies LimitedInventors: Steven John Fishwick, John Howson
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Publication number: 20220245755Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
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Patent number: 11341601Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.Type: GrantFiled: September 24, 2020Date of Patent: May 24, 2022Assignee: Imagination Technologies LimitedInventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
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Publication number: 20220139022Abstract: A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.Type: ApplicationFiled: January 19, 2022Publication date: May 5, 2022Inventors: John Howson, Steven Fishwick
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Patent number: 11263798Abstract: A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.Type: GrantFiled: May 31, 2020Date of Patent: March 1, 2022Assignee: Imagination Technologies LimitedInventors: John Howson, Steven Fishwick
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Publication number: 20220060085Abstract: A power tool comprising a housing and a brushless direct-current (BLDC) motor disposed within the housing. The motor includes a stator and a rotor rotatable relative to the stator. The power tool is configured to generate a power output from the motor such that a quotient obtained by the power output measured in Watts (Wout), divided by an input measured in Volt-Amperes (Vain), and further divided by a diameter of the motor measured in meters (m), is greater than 10 Wout/Vain/m.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: John C. Vanko, Michael K. Forster, Matthew J. Velderman, John Howson
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Publication number: 20220051363Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.Type: ApplicationFiled: October 29, 2021Publication date: February 17, 2022Inventors: John Howson, Jonathan Redshaw, Yoong Chert Foo
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Publication number: 20220036642Abstract: A graphics processing system performs hidden surface removal and texturing/shading on fragments of primitives. The system includes a primary depth buffer (PDB) for storing depth values of resolved fragments, and a secondary depth buffer (SDB) for storing depth values of unresolved fragments. Incoming fragments are depth tested against depth values from either the PDB or the SDB. When a fragment passes a depth test, its depth value is stored in the PDB if it is a resolved fragment (e.g. if it is opaque or translucent), and its depth value is stored in the SDB if it is an unresolved fragment (e.g. if it is a punch through fragment). This provides more opportunities for subsequent opaque objects to overwrite punch through fragments which passed a depth test, thereby reducing unnecessary processing and time which may be spent on fragments which ultimately will not contribute to the final rendered image.Type: ApplicationFiled: October 17, 2021Publication date: February 3, 2022Inventor: John Howson