Abstract: A method for providing a programmable electrostatic discharge (ESD) protection device is provided. The method includes providing a source diffusion in a substrate, providing a deeper body diffusion in the substrate, providing a gate at a space between the source diffusion and the body diffusion, and providing a variable structure for shorting the source diffusion and the body diffusion to each other when ESD voltage is encountered on a circuit connected thereto, wherein the variable structure comprises a plurality of contacts over the source diffusion for the source diffusion to be grounded to the body diffusion.

Abstract: A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: A method of providing a CMOS output stage is disclosed. The method includes providing a substrate, providing at least two wells above the substrate, providing a plurality of slots through the at least two wells into the substrate, oxidizing each of the plurality of slots, and filling each of the plurality of slots with a metal to provide a plurality of power busses. This allows power busses to be established wherever necessary without causing any circuit issues since the power buss metal is isolated by the oxide. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector.

Abstract: An electrostatic discharge (ESD) protection device is disclosed. The ESD protection device comprises a source diffusion in a substrate and a deeper body diffusion in the substrate. The ESD protection device further includes a gate function provided at a space between the source diffusion and the body diffusion surface terminations; and further includes a drain located a predetermined distance from the body diffusion. Finally, the ESD protection device includes a structure for shorting the source and the body diffusion to each other and to ground at variable distances from the channel region, thus providing a programmable variable snap back voltage to provide a protection when an ESD voltage is encountered.

Abstract: A method and system for providing a ground strap on a semiconductor device is disclosed. The method and system comprises providing a substrate region and providing an epitaxial (EPI) layer over the substrate region. The method and system includes etching a plurality of device structures in the EPI layer and providing a slot in the semiconductor substrate that is in contact with the substrate region. Finally, the method and system includes oxidizing the slot except at the bottom of the slot and providing a metal within the slot.

Abstract: A solar cell is provided comprising a substrate having a light-receiving first surface and a variegated second surface, the second surface having at least first and second recesses. The substrate is doped within the first recess to provide a p-type region, and within the second recess to provide an n-type region. At least one conductive material is disposed in each of the first and second recesses, permitting electrical connections to the p-type and n-type regions. In a first embodiment, using selective deposition, tungsten fills the slots and slots may have a depth of up to 60 microns. In a second embodiment, a sputtering technique is used to deposit metal in the slots, and slots may have a depth of up to about 10 microns.

Abstract: In one embodiment of the invention, a P buried region is formed in an N epitaxial layer and isolated from a P substrate by an N buried region. P+ emitters and P+ collectors are formed in the surface of the N epitaxial layer (acting as a base). The P buried region acts as a catch diffusion for minority hole carriers injected into the epitaxial layer by the surface emitters that escape collection by the surface P+ collectors and which would otherwise be injected into the substrate. The N buried region effectively isolates the P buried region from the P substrate and further blocks any minority carriers from being injected into the substrate. The P buried region also prevents the formation of a parasitic PNP transistor to the substrate of the integrated device. This further reduces substrate current and thus further reduces the possibility of noise and latchup.