Abstract: Cu interconnects are provided with a combined capping layer and ARC. The capping layer prevents Cu diffusion while the ARC minimizes reflectivity thereby enhancing the accuracy of subsequent photolithography. Embodiments include filling a damascene opening with Cu or a Cu alloy, planarizing, depositing a silicon nitride capping layer and then depositing a silicon oxynitride ARC on the silicon nitride capping layer.

Abstract: A semiconductor metalization barrier, and manufacturing method therefor, is provided which is deposited from an aqueous solution containing the Period 4 transition metals of chromium, nickel, and copper deposited on a palladium-activated copper bonding pad.

Abstract: A semiconductor device is provided with a tantalum layer to line the channels and vias of a semiconductor, a tungsten nitride layer at a low temperature on the tantalum layer, and a copper conductor layer on the tungsten nitride layer. The tungsten nitride acts as a highly efficient copper barrier material with high resistivity while the tantalum layer acts as a conductive barrier material to reduce the overall resistance of the barrier layer.

Abstract: A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to deposit a large grain conductive layer in the channel.

Abstract: A semiconductor metalization barrier, and manufacturing method therefor, is provided which is deposited from an aqueous solution containing the Period 4 transition metals of chromium, nickel, and copper deposited on a palladium-activated copper bonding pad.

Abstract: A method is provided for forming seed layers in a channel or via by applying a high bias to the material of the seed layer during deposition. This sputters off the seed layer overhang in order to reduce the electrical resistance of the seed layer, maintain its barrier effectiveness and enhance the subsequent filling of the channel or via by conductive materials.

Abstract: A new type of plasma coil for use in ionized metal plasma deposition systems. This new coil provides significant added strength to prevent sagging or other mechanical deformation. The improved coil consists of a core of a high strength material such as Titanium, for example. The rigid core is surrounded on all sides by a layer of pure copper. The rigid core could be made of other refractory metals. A Titanium copper alloy core could be used and would bind the Titanium to the copper within the core to prevent it from diffusing or reacting with the pure copper outer layer.

Abstract: An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.

Abstract: A method is provided for forming adhesion/barrier/conductor layers on semiconductor wafers in vias by using a high temperature adhesion/barrier material deposition step. The adhesion/barrier material is deposited over a channel conductor in the semiconductor dielectric with the semiconductor wafer at high temperature over 400° C., the temperature is reduced below 150° C., and then seed material is deposited so it is not exposed to temperatures above 150° C. which cause agglomeration.

Abstract: A method is provided for forming seed layers in semiconductor device channels or vias by using an inert gas sputter etching technique. The technique etches back the seed layers which results in a reduction of seed layer overhang at the top of the channels or vias, thereby enhancing the subsequent filling of the channel or vias by conductive materials.

Abstract: A system and method for etching structures in a layer of a semiconductor device are disclosed. The method and system include spinning-on a hardmask layer, patterning the hardmask layer, and etching the layer. The hardmask layer is disposed above the layer and has a high etch selectivity.

Abstract: This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curing oven, optionally containing an inert gas, and pre-heated to a temperature below which excessive thermomechanical stresses and/or oxidation are not created in the semiconductor wafer. The temperature within the curing oven is then raised to a curing temperature, and thereafter the temperature is slowly lowered to prevent the formation of stress cracks and the loss of dielectric function of the thin film. The curing method of this invention is useful for the manufacture of semiconductor devices employing a variety of spin-on materials.

Abstract: A method is provided for forming seed layers in semiconductor channel and via openings by using a two-stage approach after lining the channel and via openings with barrier material. First, a low temperature deposition of a seed layer is performed at below the 250° C. at which conductive material agglomeration occurs. Second, a higher temperature deposition of a seed layer is performed at above 250° C. Then, the conductive material is deposited to fill the channel and via openings.

Abstract: A method for producing a dielectric layer in a semiconductor product includes two steps. The first step is forming a fluorinated layer (e.g. SiOF or fluorosilicate glass ("FSG")) which includes a material formed in part with fluorine. The second step is forming a fill layer (e.g. SiO.sub.2) above the fluorinated layer. The fill layer is substantially free of materials formed in part with fluorine. A top surface of the fill layer can be planarized. Surface treatments and oxide caps can be applied to the planarized surface to form fluorine barriers if part of the fluorinated layer is exposed to higher layers. Such a method, and a semiconductor device or integrated circuit manufactured according to the method, allow the dielectric constant of an inter-layer dielectric ("ILD") to be lowered while also minimizing the complexity and expense of the manufacturing process.

Abstract: Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A metal, such as tungsten, is subsequently deposited to fill the borderless via. Embodiments include thermal decomposition of an organic-titanium compound, such as tetrakis-dimethylamino titanium, and treating the deposited titanium nitride in an H.sub.2 /N.sub.2 plasma to lower its resistivity.

Abstract: A method is provided for manufacturing a semiconductor device by: depositing a tantalum layer to line the channels and vias of a semiconductor; depositing a tungsten nitride layer at a low temperature on the tantalum layer; and depositing a copper conductor layer on the tungsten nitride layer. The tungsten nitride acts as a highly efficient copper barrier material with high resistivity while the tantalum layer acts as a conductive barrier material to reduce the overall resistance of the barrier layer.

Abstract: An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.

Abstract: A method is provided for forming barrier layers in channel or via openings of semiconductors by using in-situ nitriding of barrier metals (Ta, Ti, or W) after they have been deposited in channel and via openings which will allow better control of the barrier metal/barrier material (Ta/TaN, Ti/TiN, or W/WN) composition, eliminate particle problems, and avoiding target poisoning.

Abstract: A method for implanting copper conductive layers in channel or via openings with alloying elements, such as magnesium, boron, tin, and zirconium. The implantation is performed after conductive layer chemical-mechanical-polishing (CMP) using a surface barrier layer as an implant barrier. With the surface barrier layer being removed by barrier layer CMP, this allows directed, heavy implantation of the conductive layer with the alloying elements.

Abstract: A method and a system are provided for plating workpieces as part of an "on-track" in-line or a radially arranged manufacturing system, including "on-site" measurement of at least one plating characteristic for computer controlled process regulation and quality control. Movement of workpieces between various stations is controlled in response to a comparison of the measured value(s) of the plating characteristic(s) and (a) target value(s) or target range(s) of values.