Abstract: A power amplifier circuit includes a main amplifier circuit having a main amplifier for amplifying an input signal in one of a full-power mode and at least a back-off mode. A first peak amplifier circuit is in parallel with the main amplifier circuit. The first peak amplifier circuit has a peak amplifier in series with a transmission line. The peak amplifier is configured to be activated in the full-power mode and to be de-activated in at least the back-off mode. A combining node is connected to an output of the main amplifier circuit and an output of the transmission line. In some embodiments, a matching network is connected at the output of the combining node. In some embodiments, the transmission line is selected so the first peak amplifier circuit appears substantially as an open circuit to the combining node.

Abstract: A power amplifier circuit includes a main amplifier circuit having a main amplifier for amplifying an input signal in one of a full-power mode and at least a back-off mode. A first peak amplifier circuit is in parallel with the main amplifier circuit. The first peak amplifier circuit has a peak amplifier in series with a transmission line. The peak amplifier is configured to be activated in the full-power mode and to be de-activated in at least the back-off mode. A combining node is connected to an output of the main amplifier circuit and an output of the transmission line. In some embodiments, a matching network is connected at the output of the combining node. In some embodiments, the transmission line is selected so the first peak amplifier circuit appears substantially as an open circuit to the combining node.

Abstract: Amplifier units and methods of use are described herein. A amplifier unit includes a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.

Abstract: Amplifier units and methods of use are described herein. A amplifier unit includes a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.

Abstract: The present disclosures an amplification unit which comprises a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.

Abstract: The present disclosures an amplification unit which comprises a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.

Abstract: A digital power amplifier (or power switching amplifier or power switch) for use in a digital transmitter includes a low impedance multi-stage driver circuit having a low impedance pre-driver and a low impedance driver. The drive circuit drives a power switch stage having two power transistors configured in a current mode class-D push-pull configuration. Utilization of gallium nitride (GaN) transistors or pseudomorphic high electronic mobility transistors (pHEMT) (or combination thereof) and sizing the transistors progressively larger in the driver than in the pre-driver (at least about 3×) provides a reduction in output impedance of the driver circuit and progressive increases in the power driving capability of the succeeding stage. This allows the use of a power amplifier at higher frequencies without altering or affecting the power efficiency and allows use of a digital power amplifier for a digital transmitter.

Abstract: The present disclosures an amplification unit which comprises a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.

Abstract: A digital power amplifier (or power switching amplifier or power switch) for use in a digital transmitter includes a low impedance multi-stage driver circuit having a low impedance pre-driver and a low impedance driver. The drive circuit drives a power switch stage having two power transistors configured in a current mode class-D push-pull configuration. Utilization of gallium nitride (GaN) transistors or pseudomorphic high electronic mobility transistors (pHEMT) (or combination thereof) and sizing the transistors progressively larger in the driver than in the pre-driver (at least about 3×) provides a reduction in output impedance of the driver circuit and progressive increases in the power driving capability of the succeeding stage. This allows the use of a power amplifier at higher frequencies without altering or affecting the power efficiency and allows use of a digital power amplifier for a digital transmitter.

Abstract: The present disclosures an amplification unit which comprises a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.

Abstract: A power efficient system and method for linear signal power amplification are provided. A linear power amplifier provides signal amplification from a system input to a system output and is drain-modulated with a power supply signal. An active compensation circuit generates the power supply signal, which is substantially proportional to an envelope of the system input, and provides it to the power amplifier through a low-impedance output. The active compensation circuit reduces noise in the system output spectrum.

Abstract: A variable capacitance and control system used in a compensative manner to improve efficiency in power amplifier arrangements arranged to receive a power input which is voltage-modulated responsive to at least one control signal representative of the data signal. Also included are methods and software for controlling said power amplifier arrangements including the variable capacitance and control system. The data input to the power amplifier is pre-distorted and the resulting power amplification is substantially linear. The arrangement may be used in wireless base station transmitters, for example. Improved data transmission services are also provided which make use of such power amplifiers.

Abstract: The present invention deals with the problems related to thermal runaway and over-voltage breakdown in integrated circuits using a series of power transistors interconnected in a parallel circuit arrangement. The general technique described consists of a protection scheme that involves the application of a fusible material to form ballast resistor components. These components are connected in series with each of the transistors in the integrated circuits. The main advantages are significant area and cost savings in the manufacturing of the integrated circuits as well as an increase in their yield, thereby reducing costly field maintenance and equipment returns.

Abstract: A gate controlled lateral bipolar junction transistor (GCLBJT) device for an integrated circuit and a method of fabrication thereof are provided. The GCLBJT resembles a merged field effect transistor and lateral bipolar transistor, i.e. a lateral bipolar transistor having base, emitter and collector terminals and a fourth terminal for controlling a gate electrode overlying an active base region. The device is operable as an electronically configurable lateral transistor. Advantageously a heavily doped buried layer provides a base electrode having a base contact which surrounds and encloses the collector. The surface region between emitter and collector is characterized by lightly doped regions adjacent and contiguous with the heavily doped emitter and collector, which effectively reduce the base width of the bipolar transistor and improve operation for analog applications.