Abstract: A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.

Abstract: Embodiments of the present invention generally provide an improved technique to handle I/O address translation cache misses caused by I/O commands within a CPU. For some embodiments, CPU hardware may buffer I/O commands that cause an I/O address translation cache miss in a command queue until the I/O address translation cache is updated with the necessary information. When the I/O address translation cache has been updated, the CPU may reissue the I/O command from the command queue, translate the address of the I/O command at a convenient time, and execute the command as if a cache miss did not occur. This way the I/O device does not need to handle an error response from the CPU, the I/O command is handled by the CPU, and the I/O command is not discarded.

Abstract: Methods and apparatus for transferring data from a processing device to an I/O device via a data transfer buffer are provided. By signaling to an I/O device that data is available before an entire block size to be read out is written, the I/O device may begin read operations while the write is completed, thereby reducing latency. Latency may also be reduced by signaling the processing device that the buffer may be written to before the entire block size of data has been read by the I/O device, allowing the processor to begin writing the next block of data.

Abstract: The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled.

Abstract: Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. If address translation entries for a command are not found, the translation entries may be retrieved from memory. Address translations for subsequent commands depending from the command getting the miss may be preserved until the address translation entry is retrieved from memory. Therefore, retranslation of addresses for subsequent commands is avoided.

Abstract: Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue while handling multiple translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs while an outstanding miss is being handled, the pipeline may be stalled and the command causing the second miss and all subsequent commands may be processed again after the first miss is handled.

Abstract: A method and apparatus are provided for implementing transfer ordering in a processor input/output (I/O) interface. A pointer field is added to a command buffer. Commands are chained together in a linked list defining the transfer ordering. A currently executing command, or a command whose data is currently being transferred is held in a current execution register. The current execution register includes a pointer to the next command to be executed, or data to be transferred. When the current command completes, the pointer is used to fetch information for a next command. A command that last received an ordering event is held in a last received register. The last received register contains a link pointer field, which initially is not valid. When the next ordering event occurs, the link pointer field is loaded with a pointer to the command corresponding to the new ordering event. The register information is then written to the command buffer.

Abstract: In an aspect, a first method of allocating an object is provided. The first method includes the steps of (1) providing a plurality of registers coupled together to form a ring such that an output of a last register of the plurality of registers is coupled to an input of a first register of the plurality of registers; (2) employing one or more of the plurality of registers to store respective pointers to corresponding free objects; (3) every time period, rotating pointers stored in the ring such that a pointer stored in a current register of the ring is stored in a next consecutive register of the ring and a pointer stored in the last register of the ring is stored in the first register of the ring; and (4) allocating an object based on a pointer output from the last register of the ring. Numerous other aspects are provided.

Abstract: A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.

Abstract: Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue while handling translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs the relevant translation cache entries may be retrieved from memory. After the relevant entries are retrieved a notification may be sent requesting reissue of the command getting the translation cache miss.

Abstract: A method and apparatus for the prevention of unwanted access to secure areas of memory during the POR or boot sequence of a CPU. Via control within the CPU, commands that are sent to and received by the CPU prior to the finish of the POR sequence can be denied I/O address translation, thus protecting memory during the POR sequence. Furthermore, an error response can be generated in the CPU and sent back to the I/O device which issued the command.

Abstract: Methods and apparatus for tracking dependencies of commands to be executed by a command processor are provided. By determining the dependency of incoming commands against all commands awaiting execution, dependency information can be stored in a dependency scoreboard. Such a dependency scoreboard may be used to determine if a command is ready to be issued by the command processor. The dependency scoreboard can also be updated with information relating to the issuance of commands, for example, as commands complete.

Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.

Abstract: An I/O address translation apparatus and method for specifying relaxed ordering for I/O accesses are provided. With the apparatus and method, storage ordering (SO) bits are provided in an I/O address translation data structure, such as a page table or segment table. These SO bits define the order in which reads and/or writes initiated by an I/O device may be performed. These SO bits are combined with an ordering bit, e.g., the Relaxed Ordering Attribute bit of PCI Express, on the I/O interface. The weaker ordering indicated either in the I/O address translation data structure or in the I/O interface relaxed ordering bit is used to control the order in which I/O operations may be performed.

Abstract: A system for authentication to support secure data transfer includes a protocol wherein a certificate payload, an ID payload, and a signature payload all respectively contain at least two certificates, IDs, and signatures, concatenated together. The certificates are generated by different certificate authorities (CA) that have no trust relationship with each other. One certificate can be granted to a person and another to a particular host computer intended to be used by the person, so that for secure data transfer to take place, both a certified user and a certified host computer must be involved.

Abstract: In a first aspect, a first method is provided for managing system resource allocation. The first method includes the steps of (1) receiving a first command that requires a system resource; (2) receiving a first request for the system resource for the first command; (3) receiving a second command that requires the system resource; (4) assigning the system resource to the second command; and (5) receiving a second request for the system resource for the second command. Numerous other aspects are provided.

Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) receiving a set of data; (2) determining whether a free group entry of a size required by a portion of the set of data exists in one of a plurality of sections of a memory; (3) if a free group entry of the size required by the portion of the set of data does not exist in one of the plurality of sections of the memory, determining whether the memory includes one or more sections of an unallocated size; and (4) if the memory includes one or more sections of an unallocated size, allocating one of the sections of an unallocated size to the size required by the portion of the set of data thereby creating a section of a dynamically allocated size. Numerous other aspects are provided.

Abstract: Disclosed is an apparatus and method for granting guaranteed bandwidth between one or more data transmission priority requesting sources and one or more resources upon request. Data sources that do not request an assigned bandwidth are served on a “best efforts” basis. The system allows additional bandwidth to priority requesting sources when it is determined that the resource and/or the communication path to the resource is under-utilized. The system further allows the granted bandwidth to be shared by more than one source in a multiprocessor system.

Abstract: A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.

Abstract: A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.