Patents by Inventor John Iselin Woodfill
John Iselin Woodfill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8872897Abstract: A system for computing one or more calibration parameters of a camera is disclosed. The system includes a processor and a memory. The processor is configured to provide a first object either marked with or displaying three or more fiducial points. The fiducial points have known 3D positions in a first object reference frame. The processor is further configured to provide a second object either marked with or displaying three or more fiducial points. The fiducial points had known 3D positions in a second object reference frame. The processor is further configured to place the first object and the second object in a fixed position such that the fiducial point positions of the first and second objects are non-planar. The processor is further configured to compute one or more calibration parameters of the second camera using computations based on images taken of the fiducials.Type: GrantFiled: May 11, 2011Date of Patent: October 28, 2014Assignee: Intel CorporationInventors: Etienne Grossmann, John Iselin Woodfill, Gaile Gibson Gordon
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Patent number: 8743214Abstract: A system for determining one or more camera calibration parameters is disclosed. The system comprises a processor and a memory. The processor is configured to: a) provide a first pattern for display on a display screen; b) receive a first image from a camera viewing the display screen; c) provide a second pattern for display on the display screen; and d) receive a second image from the camera viewing the display screen. The relative position of the display screen and the camera are the same as when the first image was captured using the camera. The processor is further configured to determine an image location which is a projection of a known physical location on the display screen by using at least in part a first feature identified in the first image and a second feature identified in the second image and determine one or more calibration parameters based at least in part on the determined image location. The memory is coupled to the processor and configured to provide the processor with instructions.Type: GrantFiled: May 11, 2011Date of Patent: June 3, 2014Assignee: Intel CorporationInventors: Etienne Grossmann, John Iselin Woodfill, Gaile Gibson Gordon
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Patent number: 8724885Abstract: A system is disclosed. An input interface is configured to receive pixel data from two or more images. A pixel handling processor disposed on the substrate is configured to convert the pixel data into depth and intensity pixel data. In some embodiments, a foreground detector processor disposed on the substrate is configured to classify pixels as background or not background. In some embodiments, a projection generator disposed on the substrate is configured to generate a projection in space of the depth and intensity pixel data.Type: GrantFiled: December 21, 2009Date of Patent: May 13, 2014Assignee: Intel CorporationInventors: John Iselin Woodfill, Ronald John Buck, Gaile Gibson Gordon, David Walter Jurasek, Terrence Lee Brown
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Patent number: 8717450Abstract: A precision motion platform carrying an imaging device under a large-field-coverage lens enables capture of high resolution imagery over the full field in an instantaneous telephoto mode and wide-angle coverage through temporal integration. The device permits automated tracking and scanning without movement of a camera body or lens. Coupled use of two or more devices enables automated range computation without the need for subsequent epipolar rectification. The imager motion enables sample integration for resolution enhancement. The control methods for imager positioning enable decreasing the blur caused by both the motion of the moving imager or the motion of an object's image that the imager is intended to capture.Type: GrantFiled: September 14, 2012Date of Patent: May 6, 2014Assignee: Interval Licensing LLCInventors: Henry H. Baker, John Iselin Woodfill, Pierre St. Hilaire, Nicholas R. Kalayjian
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Patent number: 8639024Abstract: A system for generating disparity results comprises an interface, a first memory, a second memory, and a processor. The interface is for receiving a first element of a first set of image data and a first element of a second set of image data. The first memory is for storing the first element of the first set of image data. The second memory is for storing the first element of the second set of image data. The processor is for generating a disparity result for a first element before all elements of the first data set and the second data set have been received. The disparity result is generated using a low latency image processing system that processes a plurality of elements of the first set of image data and a plurality of elements of the second set of image data.Type: GrantFiled: August 1, 2012Date of Patent: January 28, 2014Assignee: Intel CorporationInventors: John Iselin Woodfill, Henry Harlyn Baker, Brian Von Herzen, Robert Dale Alkire
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Publication number: 20130101160Abstract: A system for generating disparity results comprises an interface, a first memory, a second memory, and a processor. The interface is for receiving a first element of a first set of image data and a first element of a second set of image data. The first memory is for storing the first element of the first set of image data. The second memory is for storing the first element of the second set of image data. The processor is for generating a disparity result for a first element before all elements of the first data set and the second data set have been received. The disparity result is generated using a low latency image processing system that processes a plurality of elements of the first set of image data and a plurality of elements of the second set of image data.Type: ApplicationFiled: August 1, 2012Publication date: April 25, 2013Applicant: TYZX, INC.Inventors: John Iselin Woodfill, Henry Harlyn Baker, Brian Von Herzen, Robert Dale Alkire
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Publication number: 20120287287Abstract: A system for determining one or more camera calibration parameters is disclosed. The system comprises a processor and a memory. The processor is configured to: a) provide a first pattern for display on a display screen; b) receive a first image from a camera viewing the display screen; c) provide a second pattern for display on the display screen; and d) receive a second image from the camera viewing the display screen. The relative position of the display screen and the camera are the same as when the first image was captured using the camera. The processor is further configured to determine an image location which is a projection of a known physical location on the display screen by using at least in part a first feature identified in the first image and a second feature identified in the second image and determine one or more calibration parameters based at least in part on the determined image location. The memory is coupled to the processor and configured to provide the processor with instructions.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: TYZX, INC.Inventors: Etienne Grossmann, John Iselin Woodfill, Gaile Gibson Gordon
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Publication number: 20120287240Abstract: A system for computing one or more calibration parameters of a camera is disclosed. The system comprises a processor and a memory. The processor is configured to provide a first object either marked with or displaying three or more fiducial points. The fiducial points have known 3D positions in a first object reference frame. The processor is further configured to provide a second object either marked with or displaying three or more fiducial points. The fiducial points had known 3D positions in a second object reference frame. The processor is further configured to place the first object and the second object in a fixed position such that the fiducial point positions of the first and second objects are non-planar. The processor is further configured to compute one or more calibration parameters of the second camera using computations based on images taken of the fiducials.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: TYZX, INC.Inventors: Etienne Grossmann, John Iselin Woodfill, Gaile Gibson Gordon
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Patent number: 8260040Abstract: A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board.Type: GrantFiled: March 2, 2011Date of Patent: September 4, 2012Assignee: Tyzx, Inc.Inventors: John Iselin Woodfill, Henry Harlyn Baker, Brian Von Herzen, Robert Dale Alkire
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Patent number: 8238611Abstract: A system for distance calculation is disclosed. The system includes an illuminator unit, one or more camera units, and a distance processor. The illuminator unit illuminates a scene in a target area using a textured pattern creator and wherein the textured pattern creator includes a diffractive optical element. The one or more camera units captures two or more images of the target area from two or more physical locations. A textured pattern illumination is visible in each of the two or more images of the target area. The images are used to calculate distances to one or more points in the scene in the target area.Type: GrantFiled: May 20, 2011Date of Patent: August 7, 2012Assignee: Tyzx, Inc.Inventors: Pierre St. Hilaire, Gaile Gibson Gordon, John Iselin Woodfill, Ronald John Buck, Steve Clohset
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Publication number: 20110222736Abstract: A system for distance calculation is disclosed. The system includes an illuminator unit, one or more camera units, and a distance processor. The illuminator unit illuminates a scene in a target area using a textured pattern creator and wherein the textured pattern creator includes a diffractive optical element. The one or more camera units captures two or more images of the target area from two or more physical locations. A textured pattern illumination is visible in each of the two or more images of the target area. The images are used to calculate distances to one or more points in the scene in the target area.Type: ApplicationFiled: May 20, 2011Publication date: September 15, 2011Applicant: TYZX, INC.Inventors: Pierre St. Hilaire, Gaile Gibson Gordon, John Iselin Woodfill, Ronald J. Buck, Steve Clohset
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Publication number: 20110210851Abstract: A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board.Type: ApplicationFiled: March 2, 2011Publication date: September 1, 2011Applicant: Tyzx, Inc.Inventors: John Iselin Woodfill, Henry Harlyn Baker, Brian Von Herzen, Robert Dale Alkire
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Patent number: 7970177Abstract: A system for distance calculation is disclosed. The system includes an illuminator unit, one or more camera units, and a distance processor. The illuminator unit illuminates a scene in a target area using a textured pattern creator and wherein the textured pattern creator includes a diffractive optical element. The one or more camera units captures two or more images of the target area from two or more physical locations. A textured pattern illumination is visible in each of the two or more images of the target area. The images are used to calculate distances to one or more points in the scene in the target area.Type: GrantFiled: March 22, 2007Date of Patent: June 28, 2011Assignee: Tyzx, Inc.Inventors: Pierre St. Hilaire, Gaile Gibson Gordon, John Iselin Woodfill, Ronald J. Buck, Steve Clohset
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Patent number: 7925077Abstract: A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board.Type: GrantFiled: January 30, 2009Date of Patent: April 12, 2011Assignee: Tyzx, Inc.Inventors: John Iselin Woodfill, Henry Harlyn Baker, Brian Von Herzen, Robert Dale Alkire
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Publication number: 20100104175Abstract: A system is disclosed. An input interface is configured to receive pixel data from two or more images. A pixel handling processor disposed on the substrate is configured to convert the pixel data into depth and intensity pixel data. In some embodiments, a foreground detector processor disposed on the substrate is configured to classify pixels as background or not background. In some embodiments, a projection generator disposed on the substrate is configured to generate a projection in space of the depth and intensity pixel data.Type: ApplicationFiled: December 21, 2009Publication date: April 29, 2010Inventors: John Iselin Woodfill, Ronald John Buck, Gaile Gibson Gordon, David Walter Jurasek, Terrence Lee Brown
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Patent number: 7664315Abstract: An integrated image processor implemented on a substrate is disclosed. An input interface is configured to receive pixel data from two or more images. A pixel handling processor disposed on the substrate is configured to convert the pixel data into depth and intensity pixel data. In some embodiments, a foreground detector processor disposed on the substrate is configured to classify pixels as background or not background. In some embodiments, a projection generator disposed on the substrate is configured to generate a projection in space of the depth and intensity pixel data.Type: GrantFiled: October 31, 2005Date of Patent: February 16, 2010Assignee: Tyzx, Inc.Inventors: John Iselin Woodfill, Ronald John Buck, Gaile Gibson Gordon, David Walter Jurasek, Terrence Lee Brown
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Patent number: 7567702Abstract: A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board.Type: GrantFiled: July 21, 2005Date of Patent: July 28, 2009Assignee: Vulcan Patents LLCInventors: John Iselin Woodfill, Henry Harlyn Baker, Brian Von Herzen, Robert Dale Alkire
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Publication number: 20090136091Abstract: A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board.Type: ApplicationFiled: January 30, 2009Publication date: May 28, 2009Inventors: John Iselin Woodfill, Henry Harlyn Baker, Brian Von Herzen, Robert Dale Alkire
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Patent number: 6456737Abstract: A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board.Type: GrantFiled: August 17, 2000Date of Patent: September 24, 2002Assignee: Interval Research CorporationInventors: John Iselin Woodfill, Henry Harlyn Baker, Brian Von Herzen, Robert Dale Alkire
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Patent number: 6215898Abstract: A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board.Type: GrantFiled: April 15, 1997Date of Patent: April 10, 2001Assignee: Interval Research CorporationInventors: John Iselin Woodfill, Henry Harlyn Baker, Brian Von Herzen, Robert Dale Alkire