Patents by Inventor John J. Benoit
John J. Benoit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9297853Abstract: A test circuit within a semiconductor wafer that measures a cut-off frequency for a transistor device under test may include a radio frequency source, located within a region of the wafer, that generates a radio frequency signal. A biasing circuit, also located within the region, may provide a current bias setting to the transistor device under test. The biasing circuit receives the radio frequency signal and applies a buffered radio frequency signal to the transistor device under test. The biasing circuit generates a buffered output signal based on the transistor device under test generating a first output signal in response to receiving the applied buffered radio frequency signal. An rf power detector, within the region, receives the first output signal and the radio frequency signal, and generates an output voltage signal, wherein the cut-off frequency of the transistor device under test is determined from the generated output voltage signal.Type: GrantFiled: June 18, 2013Date of Patent: March 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: John J. Benoit, Panglijen Candra, Peng Cheng, Blaine Jeffrey Gross, Vibhor Jain, John R. Long
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Patent number: 9231087Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.Type: GrantFiled: April 2, 2015Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
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Patent number: 9224843Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.Type: GrantFiled: March 31, 2015Date of Patent: December 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: John J. Benoit, James R. Elliott, Qizhi Liu
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Publication number: 20150214344Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.Type: ApplicationFiled: April 2, 2015Publication date: July 30, 2015Inventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
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Publication number: 20150206959Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Inventors: John J. Benoit, James R. Elliott, Qizhi Liu
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Patent number: 9059234Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.Type: GrantFiled: October 22, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: John J. Benoit, James R. Elliott, Qizhi Liu
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Patent number: 9059196Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.Type: GrantFiled: November 4, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: John J. Benoit, James R. Elliot, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
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Publication number: 20150123245Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.Type: ApplicationFiled: November 4, 2013Publication date: May 7, 2015Applicant: International Business Machines CorporationInventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
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Publication number: 20150108549Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.Type: ApplicationFiled: October 22, 2013Publication date: April 23, 2015Applicant: International Business Machines CorporationInventors: John J. Benoit, James R. Elliott, Qizhi Liu
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Publication number: 20140368227Abstract: A test circuit within a semiconductor wafer that measures a cut-off frequency for a transistor device under test may include a radio frequency source, located within a region of the wafer, that generates a radio frequency signal. A biasing circuit, also located within the region, may provide a current bias setting to the transistor device under test. The biasing circuit receives the radio frequency signal and applies a buffered radio frequency signal to the transistor device under test. The biasing circuit generates a buffered output signal based on the transistor device under test generating a first output signal in response to receiving the applied buffered radio frequency signal. An rf power detector, within the region, receives the first output signal and the radio frequency signal, and generates an output voltage signal, wherein the cut-off frequency of the transistor device under test is determined from the generated output voltage signal.Type: ApplicationFiled: June 18, 2013Publication date: December 18, 2014Inventors: John J. Benoit, Panglijen Candra, Peng Cheng, Blaine Jeffrey Gross, Vibhor Jain, John R. Long
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Patent number: 8482101Abstract: A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.Type: GrantFiled: June 22, 2009Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventors: John J. Benoit, Mattias E. Dahlstrom, Mark D. Dupuis, Peter B. Gray, Anthony K. Stamper
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Patent number: 7868423Abstract: A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region.Type: GrantFiled: November 12, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: John J. Benoit, David S. Collins, Natalie B. Feilchenfeld, Michael L. Gautsch, Xuefeng Liu, Robert M. Rassel, Stephen A. St. Onge, James A. Slinkman
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Publication number: 20100320571Abstract: A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.Type: ApplicationFiled: June 22, 2009Publication date: December 23, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John J. Benoit, Mattias E. Dahlstrom, Mark D. Dupuis, Peter B. Gray, Anthony K. Stamper
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Publication number: 20100117122Abstract: A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region.Type: ApplicationFiled: November 12, 2008Publication date: May 13, 2010Inventors: John J. Benoit, David S. Collins, Natalie B. Feilchenfeld, Michael L. Gautsch, Xuefeng Liu, Robert M. Rassel, Stephen A. St Onge, James A. Slinkman
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Patent number: 4998093Abstract: An extremely reliable, easily portable perimeter alarm system. It is comprised of a light beam controlled radio transmitter and personal warning devices capable of individually warning preoccupied highway workers of the imminent danger present when an errant vehicle violates the established perimeter of a work site. This warning will allow the workers to take evasive action and potentially avoid injury and/or death. It is also the object of this invention to allow for an extremely reliable, easily portable perimeter penetration alarm system that can be utilized in other appropriate settings by security guards, military personnel, etc., and which would provide for confidential notification to such personnel that a temporarily established portable perimeter line had been violated.Type: GrantFiled: December 16, 1988Date of Patent: March 5, 1991Inventor: John J. Benoit