Patents by Inventor John J. Budnaitis

John J. Budnaitis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020021138
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Application
    Filed: November 20, 1998
    Publication date: February 21, 2002
    Inventors: JOHN J. BUDNAITIS, JIMMY LEONG
  • Patent number: 6313411
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: November 6, 2001
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: John J. Budnaitis
  • Patent number: 6184589
    Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: February 6, 2001
    Inventors: John J. Budnaitis, Paul J. Fischer, David A. Hanson, David B. Noddin, Mark F. Sylvester, William George Petefish
  • Patent number: 6046060
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: April 4, 2000
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: John J. Budnaitis
  • Patent number: 6011697
    Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: January 4, 2000
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: John J. Budnaitis, Paul J. Fischer, David A. Hanson, David B. Noddin, Mark F. Sylvester, William George Petefish
  • Patent number: 5966022
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: October 12, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: John J. Budnaitis, Jimmy Leong
  • Patent number: 5966593
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: October 12, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: John J. Budnaitis, Jimmy Leong
  • Patent number: 5909123
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: June 1, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: John J. Budnaitis
  • Patent number: 5896038
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: April 20, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: John J. Budnaitis, Jimmy Leong
  • Patent number: 5886535
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level bum-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: March 23, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: John J. Budnaitis
  • Patent number: 5879786
    Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: March 9, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: John J. Budnaitis, Paul J. Fischer, David A. Hanson, David B. Noddin, Mark F. Sylvester, William George Petefish
  • Patent number: 5830565
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: November 3, 1998
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: John J. Budnaitis
  • Patent number: 5766979
    Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: June 16, 1998
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: John J. Budnaitis