Patents by Inventor John J. Budnaitis
John J. Budnaitis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020021138Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: ApplicationFiled: November 20, 1998Publication date: February 21, 2002Inventors: JOHN J. BUDNAITIS, JIMMY LEONG
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Patent number: 6313411Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: GrantFiled: December 9, 1997Date of Patent: November 6, 2001Assignee: W. L. Gore & Associates, Inc.Inventor: John J. Budnaitis
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Patent number: 6184589Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.Type: GrantFiled: November 18, 1998Date of Patent: February 6, 2001Inventors: John J. Budnaitis, Paul J. Fischer, David A. Hanson, David B. Noddin, Mark F. Sylvester, William George Petefish
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Patent number: 6046060Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: GrantFiled: April 17, 1998Date of Patent: April 4, 2000Assignee: W. L. Gore & Associates, Inc.Inventor: John J. Budnaitis
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Patent number: 6011697Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.Type: GrantFiled: November 18, 1998Date of Patent: January 4, 2000Assignee: W. L. Gore & Associates, Inc.Inventors: John J. Budnaitis, Paul J. Fischer, David A. Hanson, David B. Noddin, Mark F. Sylvester, William George Petefish
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Patent number: 5966022Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: GrantFiled: November 8, 1996Date of Patent: October 12, 1999Assignee: W. L. Gore & Associates, Inc.Inventors: John J. Budnaitis, Jimmy Leong
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Patent number: 5966593Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: GrantFiled: November 8, 1996Date of Patent: October 12, 1999Assignee: W. L. Gore & Associates, Inc.Inventors: John J. Budnaitis, Jimmy Leong
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Patent number: 5909123Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: GrantFiled: November 8, 1996Date of Patent: June 1, 1999Assignee: W. L. Gore & Associates, Inc.Inventor: John J. Budnaitis
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Patent number: 5896038Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: GrantFiled: November 8, 1996Date of Patent: April 20, 1999Assignee: W. L. Gore & Associates, Inc.Inventors: John J. Budnaitis, Jimmy Leong
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Patent number: 5886535Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level bum-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: GrantFiled: November 8, 1996Date of Patent: March 23, 1999Assignee: W. L. Gore & Associates, Inc.Inventor: John J. Budnaitis
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Patent number: 5879786Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.Type: GrantFiled: November 8, 1996Date of Patent: March 9, 1999Assignee: W. L. Gore & Associates, Inc.Inventors: John J. Budnaitis, Paul J. Fischer, David A. Hanson, David B. Noddin, Mark F. Sylvester, William George Petefish
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Patent number: 5830565Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: GrantFiled: November 8, 1996Date of Patent: November 3, 1998Assignee: W. L. Gore & Associates, Inc.Inventor: John J. Budnaitis
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Patent number: 5766979Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.Type: GrantFiled: November 8, 1996Date of Patent: June 16, 1998Assignee: W. L. Gore & Associates, Inc.Inventor: John J. Budnaitis