Patents by Inventor John J. Hackenberg
John J. Hackenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8258035Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).Type: GrantFiled: May 4, 2007Date of Patent: September 4, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, John J. Hackenberg, David C. Sing, Tab A. Stephens, Daniel G. Tekleab, Vishal P. Trivedi
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Patent number: 7972922Abstract: A method of forming a semiconductor layer, which in one embodiment is part of a photodetector, includes forming a silicon shape, applying ozonated water, removing the first oxide layer at a temperature below 600 degrees Celsius, and epitaxially growing germanium. The silicon shape has a top surface that is exposed. The ozonated water is applied to the top surface and causes formation of a first oxide layer on the top surface. The germanium is grown on the top surface.Type: GrantFiled: November 21, 2008Date of Patent: July 5, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Hunter J. Martinez, John J. Hackenberg, Jill Hildreth, Ross E. Noble
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Publication number: 20100129952Abstract: A method of forming a semiconductor layer, which in one embodiment is part of a photodetector, includes forming a silicon shape, applying ozonated water, removing the first oxide layer at a temperature below 600 degrees Celsius, and epitaxially growing germanium. The silicon shape has a top surface that is exposed. The ozonated water is applied to the top surface and causes formation of a first oxide layer on the top surface. The germanium is grown on the top surface.Type: ApplicationFiled: November 21, 2008Publication date: May 27, 2010Inventors: Hunter J. Martinez, John J. Hackenberg, Jill Hildreth, Ross E. Noble
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Patent number: 7687370Abstract: A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a part of the barrier layer and at least a part of the pad oxide layer are etched through the at least one opening resulting in a trench pad oxide layer. Etching of the trench pad oxide layer stops substantially at a top surface of the substrate within the isolation trench. An oxide layer is grown by diffusion on at least the top surface of the substrate corresponding to the at least one isolation trench. The method further includes etching the oxide layer and at least a portion of the substrate to form at least one isolation trench opening.Type: GrantFiled: January 27, 2006Date of Patent: March 30, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Toni D. Van Gompel, John J. Hackenberg, Rode R. Mora, Suresh Venkatesan
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Patent number: 7528029Abstract: A method is provided for making a semiconductor device. In accordance with the method, a substrate (203) is provided which has first (205) and second (207) gate structures thereon. A first stressor layer (215) is formed over the substrate, and a sacrificial layer (216) is formed over the first stressor layer. A second stressor layer (219) is formed over the sacrificial layer.Type: GrantFiled: April 21, 2006Date of Patent: May 5, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Paul A. Grudowski, Darren V. Goedekc, John J. Hackenberg
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Publication number: 20080274600Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).Type: ApplicationFiled: May 4, 2007Publication date: November 6, 2008Inventors: Leo Mathew, John J. Hackenberg, David C. Sing, Tab A. Stephens, Daniel G. Tekleab, Vishal P. Trivedi
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Patent number: 7097714Abstract: The cleaning of particles from an electrostatic chuck. In one embodiment, a method of cleaning an electrostatic chuck in a processing chamber is disclosed. The method comprises directing a flow of gas across the electrostatic chuck to dislodge particles from the electrostatic chuck and removing the flow of gas and particles through an exhaust port in the processing chamber. In this embodiment, the vacuum integrity of the chamber is not compromised during the cleaning of the electrostatic chuck.Type: GrantFiled: December 18, 2003Date of Patent: August 29, 2006Assignee: Intersil Americas Inc.Inventor: John J. Hackenberg
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Patent number: 6455379Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.Type: GrantFiled: March 6, 2001Date of Patent: September 24, 2002Assignee: Fairchild Semiconductor CorporationInventors: Linda S. Brush, Jun Zeng, John J. Hackenberg, Jack H. Linn, George V. Rouse
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Publication number: 20010022379Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.Type: ApplicationFiled: March 6, 2001Publication date: September 20, 2001Applicant: Intersil CorporationInventors: Linda S. Brush, Jun Zeng, John J. Hackenberg, Jack H. Linn, George V. Rouse
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Patent number: 6246090Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.Type: GrantFiled: March 14, 2000Date of Patent: June 12, 2001Assignee: Intersil CorporationInventors: Linda S. Brush, Jun Zeng, John J. Hackenberg, Jack H. Linn, George V. Rouse
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Patent number: 5837603Abstract: A method of smoothing irregularities in a surface of a semiconductor device using flowable particles which are dispersed onto the surface of the semiconductor device. The irregularities in the surface of the semiconductor device are filled with flowable particles smaller in size than the irregularities which are to be smoothed, and the particles are thereafter heated so that they flow and fill the irregularities, forming a smooth layer of flowable particle material which does not require polishing. The flowable particles may be mixed with non-flowable particles which are encapsulated in the layer of flowable particle material to form a homogeneous layer. The non-flowable particles may be augmentors which modify the properties of the layer. The particles may be dispersed with a spin-on process.Type: GrantFiled: May 8, 1996Date of Patent: November 17, 1998Assignee: HArris CorporationInventors: Jack H. Linn, John J. Hackenberg, David A. DeCrosta
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Patent number: 5830279Abstract: A device and method for removing contaminants from semiconductor wafers and from the interior of wafer processing chambers in which the temperature inside the chambers is raised to sufficiently high levels for short time periods. In a wafer etching chamber, heat cleaning is performed after wafer removal and lessens the required frequency of other cleaning methods and in doing so reduces the time the chamber is unavailable. In a mask removal chamber, heat cleaning is performed with the wafer in the chamber and while still under vacuum conditions, thereby driving contaminants off of both the wafer and the chamber interior. The wafer cleaning is performed prior to exposure to atmospheric water vapor which can initiate corrosion.Type: GrantFiled: September 29, 1995Date of Patent: November 3, 1998Assignee: Harris CorporationInventor: John J. Hackenberg
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Patent number: 5648678Abstract: An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.Type: GrantFiled: September 21, 1994Date of Patent: July 15, 1997Assignee: Harris CorporationInventors: Patrick A. Begley, John T. Gasner, Lawrence G. Pearce, Choong S. Rhee, Jeanne M. McNamara, John J. Hackenberg, Donald F. Hemmenway