Abstract: Parallel low-level and high-level quadrature demodulators (60,62) are provided, each including high speed analog-to-digital converters (82,84) with a nominal number of bits. A signal limiter (56) upstream of the low-level demodulator (60) limits the amplitude of an input analog signal (IF IN) to a value corresponding to a predetermined signal level. An attenuator (58) upstream of the high-level demodulator (62) attenuates the input signal (IF IN) by a predetermined factor, so that the signal level into the high-level demodulator (62) is correspondingly lower than the signal level into the low-level demodulator (60). When the amplitude of the input signal (IF IN) is below a predetermined value, a digital switching and scaling unit (72) selects the output signals from the low-level demodulator (60) and extends the digital output to a larger number of bits.

Abstract: A logarithmic I.F. amplifier having a common input terminal for receiving input signals with the method of construction including a pair of channels connected in a parallel configuration, the first channel being non-attenuated for receiving an input signal at full signal strength while the second channel is attenuated for substantially reducing the power level of the input signal, the construction resulting in saturation of a plurality of successive amplifying stages of the non-attenuated channel with increasing input signal strength prior to the delayed saturation of a plurality of duplicate amplifying stages of the attenuated channel, the attenuated channel continuing to provide compressed output signal data after the saturation of the amplifying stages of the non-attenuated channel, the sum of the output signal data from the pair of channels being effected on a summation line for providing an extended dynamic range of the logarithmic I.F. amplifier.