Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

Abstract: A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A collector layer includes an inclined side surface, and a dielectric layer is positioned in a lateral direction adjacent to the inclined side surface of the collector layer. An intrinsic base is disposed over the collector layer, and an emitter is disposed over the intrinsic base. An airgap is positioned between the dielectric layer and the inclined side surface of the collector layer in the lateral direction, and an extrinsic base is positioned in the lateral direction adjacent to the intrinsic base. The extrinsic base is positioned over the airgap.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

Abstract: Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual bulk in semiconductor on insulator technology and methods of manufacture. The structure includes a heterojunction bipolar transistor formed on a semiconductor on insulator (SOI) wafer with a doped sub-collector material in a buried insulator region under a semiconductor substrate of the SOI wafer.

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.