Abstract: A master processor, such as a processor embedded in a network interface card, is coupled to a memory via a memory data bus. The master processor generates addresses for the memory and controls the reading and writing of the memory at addressed locations. A slave processor, such as an optional encryption engine, has a data input/output bus connected to the memory data bus. The master processor also controls the reading and writing of data to/from the slave processor via the memory data bus. The master processor effects data transfers from the memory to the slave processor over the data bus by generating a series of memory addresses to read the data from the memory onto the data bus. As each data word appears on the data bus, it is written into the slave processor.

Abstract: A data transfer technique employs direct memory access (DMA) logic to transfer data to a memory and simultaneously store the data into a buffer that is closely coupled to a processor, enabling the processor to access the data quicker than if accesses to the memory were required. The simultaneous transfer is selectively enabled and disabled by the processor, so that only those portions of the data that are actually needed by the processor are stored into the buffer. The technique is used on a network interface card (NIC), in conjunction with host memory interface logic that transfers packets and packet descriptors from host memory to memory on the NIC. The DMA logic is controlled through the use of DMA descriptors residing on ring data structures in the NIC memory. The processor sets the value of a flag in a descriptor to indicate whether the data involved in a DMA transfer is to be written to the buffer.

Abstract: The memory space accessible by a processor is partitioned such that multiple memory regions map to the same physical memory. Processor accesses in one of the regions are regarded as normal accesses, and are satisfied from the memory or a read buffer. If memory access is required, the processor is stalled until the desired data is returned from the memory. Processor accesses to the other region are regarded as requests to prefetch the data from the memory and place it into a read buffer without stalling the processor. The processor continues program execution while the data is being prefetched. At a later point in program execution, the processor requests the data via the first region. The data likely resides in the read buffer, and can therefore be provided to the processor quickly, resulting in improved performance.

Abstract: A bus and associated logic employ a master/slave communication protocol and unidirectional point-to-point connections. Unidirectional address lines carry address signals from a bus master to bus slaves. One set of unidirectional data lines carry data from the master to the slaves, and another set carries data from the slaves to the master. The master initiates a bus transaction by asserting a request signal and placing an address on the address lines. A slave device responds by returning an acknowledge signal. The master maintains the address and the request on the bus until one clock cycle after receiving the acknowledge signal. For a read, the data is returned in the cycle following the acknowledge signal. For a write, the master places the write data on the outgoing data lines and maintains the data value on the bus until one cycle after the acknowledge signal. Additionally, the master deasserts the request signal for at least one cycle between bus transactions.

Abstract: A method and apparatus for rapidly detecting the source of an interrupt. A multi-bit interrupt state register is provided which registers the occurrence of an interrupt in response to an interrupt event. The outputs of the interrupt state register are coupled to an interrupt vector register which is memory mapped and directly accessible to a processor via load and store instructions. The interrupt vector register is continuously updated to reflect the current state of the interrupt state register. The processor may read the interrupt vector register with low latency, store the contents of the interrupt vector register in a general purpose register within the processor, and determine the source of interrupts via bit test instructions performed on the general purpose register. The bits interrupt state register may be cleared by the processor by upon the issuance of a memory mapped write command to a clear register.