Abstract: A simplified comparator circuit (10) having hysteresis and lower power requirements for its implementation. The circuit (10) includes 2 minimum-sized MOSFETs (MN4, MN5) providing feedback from the circuit output to an input device (MN1) body to produce hystereis, requiring very little power. This invention is suitable for applications not requiring a precisely set hysteresis magnitude.

Abstract: A HDD write driver circuit (10) having a boost current overshoot programmed by a plurality of pull-up devices (MP35, MP36, MP39, MP45). The pull-up strength of an inverter (20) is adjustably selected by programming pull-up PMOS devices, and less power is dropped across a resistor (R41) such that there is less boost current overshoot when an overshoot MSB is low.

Abstract: A technique for presenting an optimally timed control signal to an upper H-switch driver in a fashion capable of achieving a very fast transition of the current in the inductive recording head. The technique also provides a current boost during the transition while resulting in minimized power consumption at other times.

Abstract: A negative supply, low-voltage supply fault detection circuit is implemented without the need for a current mirror thereby providing for the elimination of inaccuracies generally associated with a current mirror, and resulting in less power consumption when compared with known negative supply, low-voltage detection circuits that employ a current mirror and associated support circuitry.

Abstract: Undershoot and overshoot control circuitry is provided in a write driver circuit to enhance its efficiency and ability to quickly change directions of write current through a write head.

Abstract: Turn-on and turn-off control circuitry are provided for a write driver circuit having first and second switching devices for directing current in opposite directions through a write head between first and second terminals in response to first and second input signals. The turn-off control circuitry includes first and second active devices coupled to the control elements of the respective first and second switching devices. The first and second active devices are operated to pull current from the control elements of the first and second switching devices in first and second current paths upon activation of appropriate input signals. First and second resistors are connected in the respective first and second current paths. The turn-on control circuitry includes a first resistor coupled between a control element of the first switching device and a fixed voltage and a second resistor coupled between a control clement of the second switching device and the fixed voltage.

Abstract: A magnetic recording control circuit for controlling current through a magnetic recording head includes a switch network, a signal coupler, and first and second voltage clamps. The switch network is connected to first and second magnetic recording head node regions and includes first, second, third, and fourth switches each having a variable magnitude conduction path and a control region. The signal coupler includes an input region and a plurality of output regions each connected to the control region of a corresponding switch. The first and second voltage clamps limit voltage differences between the magnetic recording head node regions and the control regions of the first and second switches.

Abstract: The present invention is a dual-input-to-single-output amplifier circuit having a processing amplifier, first and second coupling regions, first and second input impedance circuits, first and second feedback impedance circuits, first and second shunting impedance circuits. The processing amplifier has first and second input regions and an output region. The first and the second input regions each exhibit a relatively high circuit impedance. The output region exhibits a relatively low circuit impedance. The processing amplifier is capable of providing at the output region a signal in a first magnitude direction substantially similar to a signal provided at the second input region in the first magnitude direction but of a greater magnitude in the first magnitude direction.

Abstract: A write driver, having a pair of head pins for connection to a write head, includes two push-pull buffer circuits connected respectively between first and second pull-up resistors and the control nodes of first and second upper drive transistors. The buffer circuits selectively charge and discharge the inherent capacitances of the upper drive transistors, thereby accelerating their turn on and turn off without diminishing head swing. Moreover, connecting the buffer circuits between the pull-up resistors and the upper transistors effectively isolates, or buffers, the pull-up resistors from the self-inductance voltages of the write head, reducing glitching in the write-head output signal.

Abstract: A multiplexer selectively connects one of first and second nodes to a third node. The multiplexer includes a first switch coupled between the first and third nodes, a second switch coupled between the second and third nodes, and a control input for receiving a signal to either open the first switch and close the second switch or open the second switch and close the first switch. Additionally, a delay circuit, coupled to the control input and the second switch, delays closure of the second switch until the first switch is open. In a preferred embodiment, the delay circuit includes two field-effect transistors having substantially different width-to-length ratios.

Abstract: A programmable phase comparator comprises a switch circuit operable in response to first and second signals to provide an output signal representative of the phase relationship of the first and second signals. A reference signal is applied to the switch circuit to offset the output signal. A phase adjustment adjusts the phase relationship of the first and second signals so that the offset output signal is representative of a null condition. The switch circuit preferably is a Gilbert multiplier having a current source, an impedance means, and a transistor circuit connected between the current source and the impedance means. The transistor circuit has first and second inputs for receiving the first and second signals. The reference signal is input between the transistor circuit and the impedance means and is connected to an output. The output provides the output signal having a value based on the reference signal and the phase relationship of the first and second signals.

Abstract: A system for writing servo information to a plurality of magnetic discs in a servo write mode, and for writing data to the plurality of magnetic discs in a data write mode in disclosed. The system includes a servo binary input buffer for receiving a mode signal and for directing the write signal based upon the mode signal. A first plurality of switches, coupled to the servo binary input buffer and to a disc select buffer, directs the write signal to a selected portion of a plurality of write heads. A second plurality of switches, coupled to the first plurality of switches, to the plurality of write heads, and to a head select buffer, supplies the write signal to one write head in the selected portion of the plurality of write heads during the data write mode, and supplies the write signal to one half of the write heads in the selected portion of the plurality of write heads during the servo write mode.

Abstract: A logic translating buffer for low voltage operation for receiving a TTL compatible signal and providing a current mode logic signal. The logic translating buffer includes an emitter coupled differential pair of NPN transistors with the common emitters each being connected to a current source. One of the transistors of the differential pair has a constant voltage bias applied to the base thereof that is equal to the sum of a forward biased PN junction, a forward biased Schottky diode, and the voltage drop across a first resistor. The other transistor of the differential pair is provided a signal that is representative of the logic level input to the translating buffer. A clamping transistor is provided for keeping the other transistor of the differential pair from saturating.

Abstract: The present invention is an improved current mirror circuit. This improved current mirror circuit includes first and second transistors of the same conductivity type and have bases connected together. The first transistor is connected between a first supply terminal and an input terminal. The second transistor is connected between a first supply terminal and an output terminal. Included is a feedback circuit for providing a voltage feedback between the input terminal and the bases of the first and second transistors. Also included is a bias circuit for providing a bias current to the feedback circuit that is based on the input current.

Abstract: A magnetic head swing clamp configured for interconnection with a read/write preamplifier of the type including a read differential transistor pair connected to an inductive head. The collectors of the transistors in the read differential transistor pair provide first and second read output signals at first and second read output terminals for connection to a read amplifier. The magnetic head swing clamp comprises a reference voltage generator which produces first and second reference voltage levels at first and second reference voltage output terminals. Positive and negative voltage clamps are electrically connected to the first and second reference voltage output terminals, respectively, and to the first and second read output terminals. The positive and negative voltage clamps clamp voltage swings in the first and second read output signals as functions of the first and second reference voltage levels.

Abstract: A read/write preamplifier configured for interconnection with a magnetic head through head contacts. The preamplifier includes a write control switching circuit electrically connected between first and second supply terminals and connected to the head contacts, for controlling current flow through the magnetic head. The switching circuit includes at least one transistor. A first PNP-type transistor is connected between the first supply terminal and the at least one transistor of the write control switching circuit, for controlling current flow to the write control switching circuit so as to cause the switching circuit to be driven between selected and unselected states. A PNP-type transistor bias circuit includes a mode-controlled current sink coupled between the first and second supply terminals and to the first PNP-type transistor.

Abstract: A translation circuit provides an output referenced to ground in response to either an ECL input or a TTL input. ECL or TTL supply voltages are selectively applied to first, second, third and fourth supply voltage terminals in accordance with the type of input signal received.

Abstract: A bit switch is provided for use in a digital-to-analog converter for providing a bit current to a summing bus. A first differential pair of switching devices are responsive to a digital input signal and provide first and second output signals to a second differential pair of switching devices that provide the bit current. First and second drive circuits are coupled between the first and second differential pair of switching devices for respectively slowing down the voltage transition of the first and second output signals for reducing glitches in the bit current.

Abstract: A voltage reference circuit for providing a temperature compensated voltage at an output thereof comprise a pair of transistor operated at different current densities for producing a first and second voltages having complementary temperature coefficients and circuitry for combining the two voltages to produce the temperature compensated voltage. A pair of load resistors are connected to the collectors of the two transistors for sourcing currents thereto and a feedback circuit, including a differential amplifier coupled to the respective collectors, provides a feedback signal for adjusting the potential on the bases thereof to maintain different current densities in the two transistors. A bias circuit operates in conjunction with the differential amplifier to bias the same in a balanced operating state whenever the currents in the transistors are substantially equal.

Abstract: The input voltage signals to a comparison circuit may vary between levels substantial equal to the first and second supply voltages (e.g. typically 5 volts and ground). A first transistor circuit is coupled to a current mirror circuit and to an output node for supplying a mirrorable current to the current mirror circuit which in turn reduces the voltage at the output node when the first input voltage approaches the upper supply voltage, and supplies a current to the output to increase the voltage thereat when the second input approaches the upper supply voltage. A second transistor circuit is also coupled to the current mirror and to the output for supplying a mirrorable current to the current mirror means so as to reduce the voltage at the output when the second input voltage approaches ground, and supplies current to the output to increase the voltage thereat when the first input voltage approaches ground.