Abstract: Systems and methods are provided to facilitate compliance with location dependent requirements, such as laws and regulations that vary from jurisdiction to jurisdiction. According to one embodiment, location information associated with a user is determined. Requirement information is then determined based on the location information. The user's compliance with the requirement information is then facilitated, such as by displaying an appropriate indication to the user.

Abstract: An expert system is used to design a computer network comprising hardware platforms, applications, data bases, user interfaces, etc. The expert system initially displays questions and receives responsive information from a user as to characteristics of backend data bases and whether copies of said backend data bases should be stored in respective frontend data bases. In response, the expert system "builds" one of a predetermined set of backend models which corresponds to the information. Next, to reduce complexity, the expert system identifies two or more of the frontend data bases of compatible type that can be merged together and then displays questions and receives responsive information indicating whether the mergers should be made. Next, the expert system displays questions and receives responsive information as to characteristics of frontend components including an intermediate server.

Abstract: A hardware logic simulation machine comprised of an array of specially designed parallel processors, with there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory. Logic values simulated by one processor are communicated to other processors by a switching mechanism controlled by a controller. If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.