Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.

Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.

Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.

Abstract: A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.

Abstract: Technology for concurrently powering equipment from multiple power sources, and the control thereof is disclosed. One example implementation of the technology includes a first power supply that powers equipment from a first power source and a second power supply that also powers the equipment from a second power source while the equipment is being powered by the first power supply. A target direct current (DC) output voltage of at least one of the power supplies is changed, thereby changing a ratio of the power being drawn from the first power supply to the power being drawn from the second power supply.

Abstract: A power supply is described herein which provides power to a load, such as a load including one or more computing devices. The power supply uses a slow-response power source (such as a fuel-driven mechanism) to handle a slow-moving component of the demand level presented by the load, and uses a fast-response power source (such as a battery or a capacitor, etc.) to handle a fast-moving component of the demand level. By virtue of this approach, the power supply can manage the load level as it appears to the slow-response power source, allowing, in turn, the slow-response power source to service even fast-changing loads—a task which it could not otherwise perform due to its native limitations.

Abstract: Systems and methods for increasing power measurement accuracy for power factor correction (PFC) are disclosed. An exemplary method may include providing a PFC circuit for a power supply, the PFC circuit having a bulk capacitor connected to a rectified AC line. The method may also include measuring output load. The method may also include enabling AC wave skipping if the measured output load drops below a threshold value.

Abstract: Systems and methods for increasing power measurement accuracy for power factor correction (PFC) are disclosed. An exemplary method may include providing a PFC circuit for a power supply, the PFC circuit having a bulk capacitor connected to a rectified AC line. The method may also include measuring output load. The method may also include enabling AC wave skipping if the measured output load drops below a threshold value.