Patents by Inventor John J. Talvacchio

John J. Talvacchio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9646259
    Abstract: A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: May 9, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Patrick B. Shea, Erica C. Folk, Daniel J. Ewing, John J. Talvacchio
  • Patent number: 9355362
    Abstract: Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: May 31, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Patrick B. Shea, Erica C. Folk, Daniel J. Ewing, John J. Talvacchio
  • Publication number: 20140357493
    Abstract: A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: PATRICK B. SHEA, ERICA C. FOLK, DANIEL J. EWING, JOHN J. TALVACCHIO
  • Patent number: 8852959
    Abstract: A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 7, 2014
    Assignee: Northrup Grumman Systems Corporation
    Inventors: John J. Talvacchio, Erica C. Folk, Sean R. McLaughlin, David J. Phillips
  • Publication number: 20130157864
    Abstract: A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Inventors: John J. Talvacchio, Erica C. Folk, Sean R. McLaughlin, David J. Phillips
  • Publication number: 20130119351
    Abstract: Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Inventors: Patrick B. Shea, Erica C. Folk, Daniel J. Ewing, John J. Talvacchio
  • Patent number: 7830644
    Abstract: Methods of producing polycrystalline and single crystal dielectrics are disclosed, including dielectrics comprising CaCu3Ti4O12 or La3Ga5SiO4. Superior single crystals are manufactured with improved crystallinity by atomic lattice constant adjustments to the dielectric and to the substrate on which it is grown. Dielectric materials made according to the disclosed methods are useful for manufacture of energy storage devices, e.g. capacitors.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: November 9, 2010
    Assignee: Northop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, John J. Talvacchio, Marc Sherwin, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, John D. Adam
  • Publication number: 20080218940
    Abstract: Methods of producing polycrystalline and single crystal dielectrics are disclosed, including dielectrics comprising CaCu3Ti4O12 or La3Ga5SiO4. Superior single crystals are manufactured with improved crystallinity by atomic lattice constant adjustments to the dielectric and to the substrate on which it is grown. Dielectric materials made according to the disclosed methods are useful for manufacture of energy storage devices, e.g. capacitors.
    Type: Application
    Filed: March 5, 2007
    Publication date: September 11, 2008
    Applicant: Northrop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, John J. Talvacchio, Marc Sherwin, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, John D. Adam
  • Patent number: 5162294
    Abstract: A supported superconductor is made where a top layer of alkaline earth metal-copper oxide based material (10) is applied to a buffer layer (14) of La.sub.2-x Sr.sub.x CuO.sub.4, where x is a value from 0 to 0.4, all of which is supported by a bottom layer (12) of .alpha.-Al.sub.2 O.sub.3.
    Type: Grant
    Filed: February 28, 1991
    Date of Patent: November 10, 1992
    Assignee: Westinghouse Electric Corp.
    Inventors: John J. Talvacchio, Martin G. Forrester
  • Patent number: 5084437
    Abstract: This is a method for making an ohmic connection between a semiconductor and oxide superconductor, the connection being such that current can pass between the semiconductor and the superconductor without going through a degraded portion which is greater than the coherence length of the superconductor. The method can comprise depositing a buffer layer (which is essentially inert to the oxide superconductor) on a first portion of a semiconductor substrate, and depositing oxide superconductor on the barrier layer, and depositing a superconductor contact layer (e.g. of gold or silver) on the oxide superconductor, and depositing a semiconductor contact layer on a second portion of the semiconductor substrate (the semiconductor contact layer being, for example, of aluminum, or a refractory metal silicide); and depositing a layr (e.g.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: January 28, 1992
    Assignee: Westinghouse Electric Corp.
    Inventor: John J. Talvacchio
  • Patent number: 4768069
    Abstract: Disclosed is a superconducting Josephson junction which comprises a layer of niobium nitride on a substrate, an epitaxial layer of a pseudo-binary compound on the layer of niobium nitride, where the pseudo-binary compound has the composition about 3 atomic percent MgO--about 97 atomic percent CaO, to about 97 atomic percent MgO--about 3 atomic percent CaO, and an epitaxial layer of niobium nitride on the layer of pseudo-binary compound. Also disclosed is a method of making a Josephson junction by depositing a layer of niobium nitride onto a suitable substrate, depositing an expitaxial layer of a pseudo-binary compound onto the layer of niobium nitride, where the pseudo-binary compound has a composition of about 3 atomic percent MgO--about 97 atomic percent CaO, to about 97 atomic percent MgO--about 3 atomic percent CaO, and depositing an epitaxial layer of niobium nitride onto the layer said pseudo-binary compound.
    Type: Grant
    Filed: March 23, 1987
    Date of Patent: August 30, 1988
    Assignee: Westinghouse Electric Corp.
    Inventors: John J. Talvacchio, Alexander I. Braginski, Michael A. Janocko, John R. Gavaler