Patents by Inventor John J. Tang

John J. Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated capacitors in package-level structures, processes of making same, and systems containing same
    Patent number: 7989916
    Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: John J. Tang, Xiang Yin Zeng, Jiangqi He, Ding Hai
  • Copper plating connection for multi-die stack in substrate package
    Patent number: 7981726
    Abstract: An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventors: John J. Tang, Henry Xu, Jianmin Li, Xiang Yin Zeng
  • Integrated capacitors in package-level structures, processes of making same, and systems containing same
    Publication number: 20100059858
    Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.
    Type: Application
    Filed: November 10, 2009
    Publication date: March 11, 2010
    Inventors: John J. Tang, Xiang Yin Zeng, Jiangqi He, Ding Hai
  • Integrated capacitors in package-level structures, processes of making same, and systems containing same
    Patent number: 7670919
    Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: John J. Tang, Xiang Yin Zeng, Jiangqi He, Ding Hai
  • Dual die package with high-speed interconnect
    Patent number: 7511359
    Abstract: Embodiments of the invention relate to the construction of a dual die package with a high-speed interconnect. A package is created having a first die on a first side of a base substrate and a second die on a second side of the base substrate in opposed relation to the first die. A first copper plated interconnect is plated to the base substrate. Second copper interconnects are formed to connect the first copper plated interconnect to the first and second dice, respectively, such that the first and second dice are interconnected.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: John J. Tang, Xiang Yin Zeng, Jiangqi He