Abstract: A hierarchical tree of deterministic finite automata (DFA) is traversed and/or generated based on a set of regular expressions. The hierarchical DFA includes a root DFA linked together with a set of leaf DFAs, and possibly a set of branch DFAs. The root DFA is always active and is responsive to an input string, as are any currently active branch and leaf DFAs. When a final state or arc is reached or traversed in any active DFA, a regular expression has been matched. The branch and leaf DFAs are activated in response to the root DFA or a branch DFA reaching or traversing an activation state or arc corresponding to the branch or leaf DFA. Active branch and leaf DFAs will become inactive when a termination state or arc is reached or traversed within the branch or leaf DFA. State explosion in the hierarchical DFA can typically be avoided by selectively grouping similar portions of the regular expressions together in branch and leaf DFAs.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for identifying matches to a series of regular expressions, with the series of regular expressions including a first regular expression followed by a second regular expression, which avoids the potential overlap of characters used in matching the first and second regular expressions, while allowing individual deterministic finite automata (DFAs) to be used, whether standalone or as a merged DFA, which decreases the number of states required to represent the series of regular expressions. This potential overlap of characters can be avoided by adding marking states in a merged DFA as “divergent” in order to mask (e.g., ignore) a matching of the second regular expression for the potential overlap, or by using another DFA corresponding to the second regular expression for use during this divergent period.

Abstract: Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite packet orderings when distributing packets to be processed to different packet processing engines, may be particularly useful. For example, in response to a particular packet processing engine completing processing of a particular packet, a gather instruction is attached to the particular identifier of a particular ordered lock associated with the particular packet. If no longer needed for further processing, the packet processing engine is immediately released to be able to process another packet or perform another function. The gather instruction is typically performed in response to the particular ordered lock being acquired by the particular identifier, with the gather instruction causing the processed particular packet to be sent.

Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with cooperative flow locks distributed among multiple components, such as on different application-specific integrated circuits in a packet switching device. Flow locks are typically used for maintaining the order of packets and operations performed thereon by the coordination of a context (e.g., the processing of a packet by a packet processor) with a corresponding flow lock interface, and by the manner of communication performed among the flow lock interface and the distributed flow locks.

Abstract: Data is protected using locks, with the protected data sometimes being included in the locking messages, which may reduce overall processing latency, and/or reduce a bandwidth requirement for and/or number of storage operations accessing the native storage of the protected data. For example, the lock manager receives lock requests from each of the requesters, and selectively grants the lock requests. The protected data is typically communicated in the locking messages when the lock is highly contested, or at least two request for access to the data are pending. The lock manager initiates the sequence by indicating in a grant message to a requester to include the protected data in its release message. The lock manager then copies this data received in the release message to its grant message to the next requestor.

Abstract: Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets may be particularly useful. One implementation uses a locking request, acceptance, and release protocol. One implementation associates instructions with locking requests such that when a lock is acquired, the locking mechanism executes or causes to be executed the associated instructions as an acceptance request of the lock is implied by the association of instructions (or may be explicitly requested). In some applications, the ordering of the entire sequence of packets is not required to be preserved, but rather only among certain sub-sequences of the entire sequence of items, which can be accomplished by converting an initial root ordered lock (maintaining the sequence of the entire stream of items) to various other locks (each maintaining a sequence of different sub-streams of items).

Abstract: Methods and apparatus are disclosed using a random indication to map items to paths and to recirculate or delay the sending of a particular item when a destination over its mapped path is unreachable, including, but not limited to the context of sending of packets across multiple paths in a packet switching system. In one implementation, a set of items is buffered, with the set of items including a first and second sets of items. The items in the first set of items are forwarded over a set of paths in a first configuration. The set of paths is reconfigured into a second configuration, and the items in the second set of items are forwarded over the set of paths in the second configuration. In one implementation, a recirculation buffer is used to hold items not immediately sent. In one implementation, the paths are reconfigured in a random fashion.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for matching items with resources, such as, but not limited to packet processing contexts, output links, memory, storage, specialized hardware or software, compute cycles, or any other entity. One implementation includes means for maintaining distribution groups of items, means for maintaining differently aged resources queues, and means for matching resources identified as being at the head of the plurality of differently aged resources queues and as being primarily and secondarily associated with said distribution groups based on a set of predetermined criteria.

Abstract: Memory is shared among multiple information channels, which may be of particular use for storing streams of packets. Memory allocation information is maintained which can be used to identify the current number of memory segments (e.g., some definable amount of memory) allocated for each of the multiple channels as well as the available number of shared memory segments. Items, such as, but not limited to data, packets, etc., are received and stored in the memory according to the memory allocation information. After a first processing stage for an item, the memory allocation information is updated to reflect an expected number of available memory segments to become available for the respective channel after a subsequent second processing stage. After the second processing stage is completed for an item, its number of memory segments are de-allocated based on the expected available data. In one embodiment, these memory segments are de-allocated one at a time.

Abstract: Packets and packets fragments possibly received out of sequence are distributed into an expandable set of queues. For each particular packet or fragment, a queue within a set of queues is identified that does not contain a packet or packet fragment that is subsequent to the particular packet or fragment, and the particular packet or fragment is enqueued therein. If there is not such a queue available, a new queue is added to the set of queues. A data structure is typically updated for packet fragments to identify when all fragments have been received and the order of queues containing the packet fragments in order of their position within the reassembled packet. This ordered list of the queues is communicated to a reassembly mechanism to retrieve the packet fragments and to reassemble the packet. Resequencing of packets is similarly performed, and may be part of the reassembly process.

Abstract: The present invention provides a multithreaded processor, such as a network processor, that fetches instructions in a pipeline stage based on feedback signals from later stages. The multithreaded processor comprises a pipeline with an instruction unit in the early stage and an instruction queue, a thread interleaver, and an execution pipeline in the later stages. Feedback signals from the later stages cause the instruction unit to block fetching, immediately fetch, raise priority, or lower priority for a particular thread. The instruction queue generates a queue signal, on a per thread basis, responsive to a thread queue condition, etc., the thread interleaver generates an interleaver signal responsive to a thread condition, etc., and the execution pipeline generates an execution signal responsive to an execution stall, etc.

Abstract: Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite packet orderings when distributing packets to be processed to different packet processing engines, may be particularly useful. For example, in response to a particular packet processing engine completing processing of a particular packet, a gather instruction is attached to the particular identifier of a particular ordered lock associated with the particular packet. If no longer needed for further processing, the packet processing engine is immediately released to be able to process another packet or perform another function. The gather instruction is performed in response to the particular ordered lock being acquired by the particular identifier, with the gather instruction causing the processed particular packet to be sent.

Abstract: The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication latencies. In an upper pipeline, an instruction unit determines an instruction fetch sequence responsive to an instruction queue depth on a per thread basis. In a lower pipeline, a thread interleaver determines a thread interleave sequence responsive to thread conditions including thread latency conditions. The thread interleaver selects threads using a two-level round robin arbitration. Thread latency signals are active responsive to thread latencies such as thread stalls, cache misses, and interlocks. During the subsequent one or more clock cycles, the thread is ineligible for arbitration. In one embodiment, other thread conditions affect selection decisions such as local priority, global stalls, and late stalls.

Abstract: Methods and apparatus are disclosed for an adaptive rate control mechanism reactive to flow control messages in a packet switching system and other communications and computer systems. Typically, a multiplicative increase and exponential decrease technique is used to throttle traffic. Backpressure feedback is used to calculate the initial rate at which to allow traffic after backpressure is deasserted. This reduces the probability of underrun of buffers (e.g., too little traffic being carried). The adjustment to the initial rate is made by measuring the time between the XON and XOFF in factor periods. Then a target XON time is subtracted. If the result is positive (i.e., the measured XON time was too long), the rate is multiplicatively increased (e.g., by a factor of two to the difference). If the result is negative (i.e., the measured XON time was too short), the rate is exponentially decreased (e.g., by the square root).

Abstract: Methods and apparatus are disclosed for communicating time and latency sensitive information in a system, such as, but not limited to a computer or communications system. A first block of data is identified and transmitted. A check code is partially determined based on this first data. While the first data is being transmitted, the time-sensitive data (e.g., flow control, other control information, etc.) is identified. This identified time-sensitive data is then contiguously transmitted after the first data. The determination of the check code is completed based on the time-sensitive data, and the check code is contiguously transmitted after the time-sensitive data. One implementation receives the first data, the time-sensitive data, and the check code. If error correction is being used and is needed, the time-sensitive data is first corrected based on the check code, and then subsequently, the first data is corrected. In this manner, the latency of the availability of this time-sensitive data may be reduced.

Abstract: Traffic information is accumulated and flow control information distributed in a packet switching system. Traffic information is collected in multiple elements, which forward in a coordinated fashion to collecting elements indications of congestion and other types of information. The collecting elements manipulate the received indications and generate flow control messages which are sent to individual sending components of the packet switching system. In one implementation, a switching element maintains for each destination a count of packets within itself which are addressed to the particular destination. An indication of a portion of this collected information is included in a packet header forwarded from each of the elements each packet time. Each of the elements are assigned a different offset, such that they send an indication of a different portion of their collected information, so a view of the traffic conditions and/or buffer occupancies within a packet switching system is efficiently produced.

Abstract: Methods and apparatus are disclosed for distributing flow control information in a packet switching system. In one packet switching system, flow control information is collected in a data structure in the first stage switching elements. Each of these switching elements transmit data from the flow control data structure as small messages or in fields included in packets being sent across multiple statically allocated paths. Flow control information is received by next stage elements, which are programmed to forward only flow control information received from a limited number of components or over a limited number of paths. The first stage switching elements may also periodically or occasionally delay sending flow control information or send a dummy message or information to accommodate bandwidth transmission differences between components of the packet switching system, including to accommodate bandwidth variations caused by plesiochronous timing across the network.

Abstract: Methods and apparatus are disclosed for using barrier phases to synchronize processes and components in a packet switching system, including, for example, but not limited to the use of barrier phases in the coordinated timing of the sending of information (e.g., flow control information) within a packet switching system, and the use of barrier phases in a packet sequence number windowing protocol. In one implementation, elements are assigned to one of multiple ordered sets of a barrier groups, wherein each element of a barrier group must be set to a common barrier state before any element of a next a barrier group can switch to a next barrier state, and once all elements of a particular barrier group switch to a new barrier state, all the elements of the next barrier group begin to switch to the next barrier state.

Abstract: Methods and apparatus are disclosed for using barrier phases to limit the disorder of packets which may be used in a computer or communications system. In one packet switching system, source nodes include an indication of their current barrier state in sent packets. For each barrier state, a predetermined range of sequence numbers may be used or a predetermined number of packets may be sent by a source node. The source, destination, and switching nodes are systematically switched between barrier phases, which is typically performed continuously in response to the flow of barrier request and barrier acknowledgement packets or signals. Each source node broadcasts to all forward connected nodes a barrier request to change to a next barrier state. After a switching node has received a barrier request on all incoming links, the switching node propagates the barrier request.

Abstract: A lightweight, portable, cargo-retaining header wall is provided which serves to vertically, transversely, and securely span the interior space between opposed walls of a polygonal cargo-receiving container such as a truck trailer or railroad boxcar to prevent cargo shifting beyond the header wall. The header wall preferably includes: a bottom rollered lattice structure composed of a plurality of interconnected bars spaced just closely enough to prevent cargo movement therethrough; a jacking member; and a driving assembly mounted to the lattice structure and receiving the jacking member for incrementally moving the jacking member, the assembly having an operating lever.