Abstract: The gate of a P-channel pull-up transistor connected between an input node and a supply voltage in a buffer circuit is coupled to a test node. An N-channel pull-down transistor is connected between the input node and ground and has a gate connected to the test node. A logic low signal provided to the test node allows the circuit to operate normally. During test mode, a logic high signal is provided to the test node to turn off the P-channel pull-up transistor and thus prevent DC current flow in the circuit via the pull-up transistor. This logic high signal also turns on the pull-down transistor and, by shorting the input node to ground potential, prevents any other DC crossover currents from flowing in the circuit. Thus, during test mode, quiescent current flow resulting from small manufacturing defects in the circuit are obscured by larger DC currents and, as a result, may be readily measured to detect the presence of such small manufacturing defects.

Abstract: A buffer circuit which exhibits increased speed in transitions between binary states. A control transistor is coupled between a pull-up transistor and an input terminal. During low-to-high input signal transitions, the control transistor limits the signal swing at the input terminal such that small variations in the input terminal voltage result in larger voltage variations at the output terminal. During such transitions, the control transistor simultaneously decouples the input terminal from the pull-up transistor, thereby decoupling the input capacitance from the pull-up transistor. As a result, the speed with which the pull-up transistor can pull the output high is increased. As the number of input signal desired to be processed increases, the reduction in logic transition time becomes more significant. Some versions further include a pull-down transistor having a control terminal coupled to the gate of the pull-up transistor and to a power-down terminal.

Abstract: Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurality of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell.

Abstract: Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurlity of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell.

Abstract: A levelized simulation system includes a means for storing a model of a logic system to be simulated. The logic system has a plurality of levels of logic which are synchronously clocked. A processing system including an arithmetic logic unit sequentially tests each element of said logic system, one level of logic at a time, thus each logic element in the first level is tested with the results there stored in a state memory, after which the logic elements of the second level of the logic system are tested and so on. During each test a comparison is made to determine whether there is a defect in the logic design.

Abstract: The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.

Abstract: Apparatus is disclosed for establishing scan-ring testing circuitry and control logic therefor on CMOS integrated circuit chips which can then be tested thereby during fabrication, after wire bonding and packaging, and while assembled and connected with other components on a printed circuit board. Tri-state buffers fabricated on the IC chip within the scan-ring control circuitry facilitate the operation of the scan-ring testing circuitry in several distinct operating modes which enable the functional circuitry of the integrated circuit to be electrically isolated from the associated signal pads for testing of the functional circuitry independently of circuitry connected to the signal pads, and for testing circuitry connected to the signal pads independently of the function circuitry of the chip.

Abstract: A general purpose register including two input ports and two output ports, each port being addressed by an independent addressing circuit. The general purpose register includes a number of internal registers, and the provision of four independent addresses enables data to be written into two internal registers while data is being read out of two internal registers. The general purpose register also includes circuitry for transferring data from the input ports directly to the output ports without entering the data into the internal registers. Interchanging of bytes of data input words is also accomplished by the general purpose register. The internal registers, the four independent addressing circuits, the data transferring circuitry and additional undedicated circuitry are integrated into a single chip.

Abstract: A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Abstract: An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the "master" and the second latch element operates as the "slave" of a master/slave latch circuit.

Abstract: An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the "master" and the second latch element operates as the "slave" of a master/slave latch circuit.

Abstract: A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Abstract: An electrical discharge is applied to a wafer mounted in a wafer holder. The wafer includes at least one conducting region covered by an insulating layer. The discharge causes a conductive channel from the conductive region through the insulating layer. The conductive channel provides a relatively low impedance path suitable for conducting away electrons which are injected into the region during processing steps such as electron beam exposure.

Abstract: Electron beam apparatus is used to develop a resist coated work piece such as a semiconductor wafer which is mounted on a moveable XY table within the apparatus work chamber. A work piece holder includes an alignment device for aligning the electron beam for highly accurate beam scanning. Thereafter, the electron beam axes are correlated to the work piece axes. In correlating the axes, the electron beam is rotated whereby the beam X and Y axes are parallel to the work piece X and Y axes, respectively. The work piece axes are then correlated to the axes of the XY table by locating the table coordinates of two known positions on the wafer.

Abstract: A CMOS output circuit for an integrated circuit chip used in high speed computers is designed so that it can drive transmission line interconnects to thereby increase the speed of the transfer of signals between chips. The CMOS circuit can drive either a nonterminated transmission line, a terminated transmission line or a random wire. The output circuit enables both low power consumption and high speed to be achieved.

Abstract: Package for an LSI chip having a plurality of contact pads comprising a carrier and a cover. The carrier is formed of a base of an insulating material and has a generally planar area for receiving the chip. A cooling stud is mounted on the base and can be provided with one or more removable cooling fins. The stud is mounted on the base opposite the area for receiving the chip. Spaced leads are carried by the base and have outer extremities which extend beyond the base in a direction away from the chip and are free of the carrier and have inner extremities which are in close proximity to the area for receiving the chip. A grounding bus is carried by the carrier to facilitate electrical checking of the package.

Abstract: An electrical discharge is applied to a wafer mounted in a wafer holder. The wafer includes at least one conducting region covered by an insulating layer. The discharge causes a conductive channel from the conductive region through the insulating layer. The conductive channel provides a relatively low impedance path suitable for conducting away electrons which are injected into the region during processing steps such as electron beam exposure.

Abstract: A table positioning apparatus suitable for use in an electron beam exposure system. A movable table holds a wafer or other work piece. The table is driven by a motor in response to a motor drive signal to position the table at different locations. An optical position measuring transducer is located in fixed relation to the table to establish a reference position for the table in a local region. The transducer provides a position signal as a function of the table position in the local region. An amplifier is provided which is responsive to the position signal to produce a servo signal. A motor drive circuit provides the motor drive signal for driving the motor in response to the servo signal so that the table is driven to the reference position. At the reference position, a reset signal is provided to reset interferometers in both X and Y axes.

Abstract: A large scale integrated circuit with external integral access test circuitry having a semiconductor body with a surface. A large scale integrated circuit is formed in the semiconductor body through the surface and comprises a large number of interconnected circuit elements with a large number of input and output pads connected to the circuit elements and disposed near the outer perimeter of the semiconductor body. An integrated test circuit is formed in the semiconductor body and extends through the surface. The integrated test circuit has a plurality of probe pads carried by the semiconductor body and connected to the test circuit. The integrated test circuit is formed external of but in relatively close proximity to the large scale integrated circuit.

Abstract: An electron beam exposure system and method for use in the process of fabricating microminiature devices at high speeds. The high-speed operation is achieved with a computer providing programmed commands specifying a particular pattern to be scanned. A processor, responsive to programmed data, generates scan data a line at a time and loads a line generator. The line generator steps to each exposure location in a line to provide control signals for controlling the position of the electron beam. The starting and end positions of scan lines in both the X and Y directions may be arbitrarily selected thereby eliminating the need for scanning areas not intended to be processed.