Abstract: Performing soft error correction includes receiving a word at a soft correction engine capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results for the received word using combinations of the soft bit positions and more than one correction mode. The soft correction engine may include a Golay engine.

Abstract: A media access control (MAC) controller is disclosed for a network providing communication for network stations located at a plurality of customer premises and sharing a communication medium, each of the premises having a plurality of network stations. The MAC controller includes a virtual local area network (vLAN) controller, providing access to the communication medium for and communication among the stations located at a single customer's premises, to define a vLAN between them. A group local area network (gLAN) controller provides access to the communication medium for and communication among interfering vLANs, two vLANs being considered to be interfering when one can sense communications over the medium from a station in the other. A MAC controller is provided in at least one station in a vLAN.

Abstract: A media access control (MAC) controller is disclosed for a network providing communication for network stations located at a plurality of customer premises and sharing a communication medium, each of the premises having a plurality of network stations. The MAC controller includes a virtual local area network (vLAN) controller, providing access to the communication medium for and communication among the stations located at a single customer's premises, to define a vLAN between them. A group local area network (gLAN) controller provides access to the communication medium for and communication among interfering vLANs, two vLANs being considered to be interfering when one can sense communications over the medium from a station in the other. A MAC controller is provided in at least one station in a vLAN.

Abstract: Performing soft error correction includes receiving a word at a soft correction engine (310a, 310b) capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results (370) for the received word using combinations of the soft bit positions and more than one correction mode. The soft correction engine (310a, 310b) may include a Golay engine.

Abstract: A media access control (MAC) controller is disclosed for a network providing communication for network stations located at a plurality of customer premises and sharing a communication medium, each of the premises having a plurality of network stations. The MAC controller includes a virtual local area network (vLAN) controller, providing access to the communication medium for and communication among the stations located at a single customer's premises, to define a vLAN between them. A group local area network (gLAN) controller provides access to the communication medium for and communication among interfering vLANs, two vLANs being considered to be interfering when one can sense communications over the medium from a station in the other. A MAC controller is provided in at least one station in a vLAN.

Abstract: Performing soft error correction includes receiving a word at a soft correction engine capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results for the received word using combinations of the soft bit positions and the more than one correction modes. The soft correction engine may include a Golay engine.

Abstract: A delay line clock multiplier is disclosed for use in a communication system, in which a delay line is used as a clock multiplier for generating a higher speed clock that may be used, for example, for data sampling. The speed and timing characteristics of the clock delay line are adjusted by controlling the supply voltage to the delay line. because proper synchronization may be achieved at the higher frequencies using an oversampling synchronization approach which in turn is made possible by the delay line clock multiplier which allows for the oversampling of a signal at sub-interval increments.

Abstract: Performing soft error correction includes receiving a word at a soft correction engine (310a, 310b) capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results (370) for the received word using combinations of the soft bit positions and more than one correction mode. The soft correction engine (310a, 310b) may include a Golay engine.

Abstract: A media access control (MAC) controller is disclosed for a network providing communication for network stations located at a plurality of customer premises and sharing a communication medium, each of the premises having a plurality of network stations. The MAC controller includes a virtual local area network (vLAN) controller, providing access to the communication medium for and communication among the stations located at a single customer's premises, to define a vLAN between them. A group local area network (gLAN) controller provides access to the communication medium for and communication among interfering vLANs, two vLANs being considered to be interfering when one can sense communications over the medium from a station in the other. A MAC controller is provided in at least one station in a vLAN.

Abstract: A delay line clock multiplier is disclosed for use in a communication system, in which a delay line is used as a clock multiplier for generating a higher speed clock that may be used, for example, for data sampling. The speed and timing characteristics of the clock delay line are adjusted by controlling the supply voltage to the delay line. because proper synchronization may be achieved at the higher frequencies using an oversampling synchronization approach which in turn is made possible by the delay line clock multiplier which allows for the oversampling of a signal at sub-interval increments.