Patents by Inventor John Joseph Bastek

John Joseph Bastek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit device substrates with selective epitaxial growth thickness compensation
    Patent number: 6727567
    Abstract: Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: April 27, 2004
    Assignee: Agere Systems INC
    Inventors: John Joseph Bastek, Thomas J. Krutsick, Robert D. Plummer
  • Manufacture of dielectrically isolated integrated circuits
    Publication number: 20020092462
    Abstract: Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.
    Type: Application
    Filed: March 5, 2002
    Publication date: July 18, 2002
    Inventors: John Joseph Bastek, Thomas J. Krutsick, Robert D. Plummer
  • Manufacture of dielectrically isolated integrated circuits
    Patent number: 6409829
    Abstract: Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: John Joseph Bastek, Thomas J. Krutsick, Robert D. Plummer