Abstract: A method of forming a CMOS device and a GaN PA structure on a 100 Si substrate having a surface orientated in 111 direction and the resulting device are provided. Embodiments include forming a device with a protective layer over a portion of a Si substrate; forming a V-shaped groove in the Si substrate; forming a buffer layer, a GaN layer, an AlGaN layer and a passivation layer sequentially over the Si substrate; forming trenches through the passivation and the AlGaN layers; forming second trenches through the passivation layer; forming electrode structures over portions of the passivation layer and filling the first and second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming vias through the dielectric layer down to electrode structures and the device.

Abstract: A method of forming a CMOS device and a GaN PA structure on a 100 Si substrate having a surface orientated in 111 direction and the resulting device are provided. Embodiments include forming a device with a protective layer over a portion of a Si substrate; forming a V-shaped groove in the Si substrate; forming a buffer layer, a GaN layer, an AlGaN layer and a passivation layer sequentially over the Si substrate; forming trenches through the passivation and the AlGaN layers; forming second trenches through the passivation layer; forming electrode structures over portions of the passivation layer and filling the first and second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming vias through the dielectric layer down to electrode structures and the device.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Abstract: A FET device comprising a semiconductor substrate; diffusion regions in the substrate separated by a channel region; a gate overlapping the channel region and a portion of the diffusion regions and separated from the substrate by a gate dielectric; and a sidewall dielectric on a sidewall of the gate; and a sidewall spacer conductor on the sidewall dielectric contacting one of the diffusion regions but not both of the diffusion regions of one device is provided along with a method for its fabrication. The conductive spacer connects diffusions of adjacent devices that share a common gate electrode.